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*ACC Micro...
**ACC2051/NT PCI Single Chip Solution for Notebook Applications c96
***Info:...
***Configurations:...
***Features:
o Supports Intel P54C, Cyrix M1, and AMD K5
- Linear burst support
- 64-bit Pentium class CPU with 66 MHz bus frequency
o ACC Micro Power Management Control
- SMM/SMI support
- Individual sets of system events and break events such as for
Global Standby, Local Standby, Suspend, and Doze control.
- Dedicated external SMI trigger inputs such as for battery
monitoring, suspend/resume button, and AC power.
- Software SMI
- Warning Timer for SMI
- Patented 'Adaptive Thermal Control' with auto-control or SMI
generation
- Shadow Registers for suspend to disk
- Suspend to DRAM
- CPU/PCI/ISA individually suspend/powered-down
- Stop clock protocol, STPCLK#
- 0 Hz suspend
- PCI suspend for Warm Docking
o Mobile PC, or PC/PCI
- CLKRUN# protocol to reduce PCI power consumption
- Serialized interrupt protocol, SIN#/SOUT# for interrupt routing
in docking design
- Serialized DMA protocol for DRQ routing in docking design
o Synchronous/asynchronous PCI bus
- Synchronous PCI clock at CPUCLK/2
- Asynchronous PCI clock
- Four PCI bus masters
- Converts back to back sequential CPU to PCI memory writes to PCI
burst writes
- Bytes merge for CPU to PCI memory write
- Eight Dwords deep of CPU to PCI posted write buffers
- Four Dwords pre-fetch buffers for CPU read from PCI memory
- PCI to DRAM posting 8 Qwords deep
- PCI from DRAM pre-fetched buffers 4 Qwords deep
- Pre-snoop capability for PCI to DRAM with bandwidth of 119 MB/s
- 3V or 5V PCI bus
o Built-in DRAM controller
- Five banks of DRAM, up to 512MB main memory
- Self-Refresh DRAM support
- EDO or Fast Page Mode DRAM
- Five RAS and 12 MA lines
- Symmetrical/Asymmetrical DRAMs
- 64-bit data path to memory
- 64-bit DRAM option for individual bank
- Four Qword posted write buffers for x-1-1-1 DRAM write cycles
- Support 3V or 5V DRAM
o Built-in level 2 cache controller
- Direct mapped write back/write through
- Up to 2MB
- Burst, pipelined burst, or standard SRAM
- Cache hit read/write x-1-1-1-1-1 ... with pipelined burst SRAM
o Built-in full-blown ISA bus interface
- Integrated 8254x1, 8259x2, 8237x2
- Programmable ISA bus speed
- Independent edge/level triggered interrupt controller
- Optional Type-F DMA
- X-bus support for chip select decode
- Flash EPROM support
- Dedicated ISA cycles option to free up the PCI bus
o Integrated Fast IDE interface
- Enhanced PCI IDE
- Support master/DMA mode IDE
- Built-in 8 Dwords posted write buffer
- Built-in 8 Dwords pre-fetched buffer
- Four independently programmable register sets for IDE timing
control
o Built-in 64-bit data path
**ACC2056 ?Pentium 3.3V Notebook [no datasheet]<Jan96...
**ACC2057 PCI Notebook/Embedded Single Chip [no datasheet]<Aug96...
**ACC2066NT 486 Notebook/Embedded Single Chip [no datasheet] ?...
**ACC2086 486 VL-based System Super Chip Soluti[no datasheet] ?...
**ACC2087 Enhanced Super Chip (486 Single Chip) <Aug96...
**ACC2089 486 PCI-based System Super Chip [no datasheet] ?...
**ACC2168/GT 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2178A 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2268 ?486 [no datasheet] ?...
**ACC???? Maple/Maple-133 486-System-On-Chip [no datasheet] ?...
**
**Support Chips:
**ACC2016 Buffer and MUX Logic c96...
**ACC2020 Power Management Chip c92...
**ACC5500 Multifunction I/O Control Chip for PS2 Model 50/60 c88...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION
The 82489DX Advanced Programmable Interrupt Controller provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.
The main function of the 82489DX is to provide interrupt management
across all processors. This dynamic interrupt distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in systems with multiple I/O subsystems, where each subsystem
can have its own set of interrupts. This chip also provides
inter-processor interrupts, allowing any processor to interrupt any
processor or set of processor. Each 82489DX I/O init interrupt input
pin is individually programmable by software as either edge or level
triggered. The interrupt vector and interrupt steering information an
be specified per pin. A 32-bit wide timer is provided that can be
programmed to interrupt the local processor. the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate time slice interrupts locally to that processor. the
82489DX provides 32-bit software access to its internal
registers. Since no 82489DX register read have any side effects, the
82489DX registers can be aliased to a user read-only page for fast
user access (e.g., performance monitoring timers).
The 82489DX supports a generalized naming/addressing scheme that can
be tailored by software to fit a variety of system architectures and
usage models. It also supports 8259A compatibility by becoming
virtually transparent with regard to an externally connected 8259A
style controller, making the 8259A visible to software.
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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