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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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**SL82C470   'Mozart' 486/386 EISA chipset                     c:Dec91
***Info:...
***Configurations:...
***Features:
o   100% EISA compatible
o   20/25/33/50 MHz 80486 DX/SX CPU operation
o   25/33/40 Mhz 80386DX CPU Operation
o   Integrated write back cache controller with built-in tag comparator
o   Concurrent CPU-cache and EMA/master operations with bus snooping
o   Only ten TTL components are required
o   Complete EISA system can be built on a baby AT sized motherboard
o   Flexible cache size from 64KB to 1MB
o   Page mode DRAM operation supporting 1 to 4 banks up to 256MB
o   Video/system BIOS, shadowing and caching
o   Supports both conventional and concurrent configurations
o   Inclusive secondary cache for snoop filtering
o   Synchronous EISA bus clock
o   Transparent Gate A20 and CPU reset
o   CPU local bus device support
o   Supports 80387, 80487SX and Weitek 3167/4167 co-processors
o   Decoupled refresh without holding CPU
o   Staggered DRAM refresh to minimize power supply noise
o   Rlch set of register options to allow customization
o   Three 160-pin PQFP packages in low power and high speed 0.8um CMOS 
    Technology
**SL82C490   'Wagner' 486?              [no datasheet]               ?...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
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