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**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:
The 82485 is a second-level cache controller designed to improve the
performance of Intel486 Microprocessor systems. One 82485 cache
controller supports 64K or 128K bytes of second level cache memory
that maps to the entire 4 Gigabytes of the Intel486 microprocessor
address space. The controller is completely software transparent. One
controller plus SRAMs provides a 64K or a 128K cache. External EPROM
can be cached yet remain write protected. The 82485 is fully
compatible with the Intel486 microprocessor. All Intel486 CPU bus
cycles and timings are supported.
A complete, optional second level cache controller using the 82485 is
available as the 485Turbocache Module from Intel (data sheet order
number 240722).
2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically to interface with the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or a non-sectored configuration (one line per tag). The 82485
will directly support a nonsectored 64K data cache or a 128K sectored
data cache. Both the 64K and 128K configurations are able to map the
entire 4 gigabytes of the Intel486 microprocessor address space. The
82485 interfaces directly to the Intel486 microprocessor. All Intel-
486 CPU bus cycles and timings are supported. The 82485 also supports
0 wait state processor operation when there is a cache hit and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations. The controller is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the system bus), so it supports the same cache consistency
mechanisms as the Intel486 CPU. The controller also provides a safe
method to cache ROM BIOS through the use of a write protect pin and a
write protect strapping option.
The data cache (Static RAM) resides external to the 82485. The 82485
provides all controls for the SRAMs. No external latches or tran-
ceivers are required. The 82485 output buffers support up to eight
SRAMs. A 64K cache can be designed with only five components; nine
components for a 128K cache. Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.
The 82485 can be used to design a custom second level cache
configuration. For an easier system design and higher integration, the
82485M Turbocache can be used (see data sheet order number 240722).
This module is a complete second level cache in one package. It
consists of a single 82485 cache controller and SRAM to provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99
***Info:
The single chipset, SiS540, provides a high performance/low cost
Desktop solution for the Super Socket 7 series CPUs based system by
integrating a high performance North Bridge, advanced hardware 2D/3D
GUI engine and Super-South bridge. In addition, SiS540 provides
system-on-chip solution that complies with Easy PC Initiative which
supports Instantly Available/OnNow PC technology, USB, Legacy Removal
and Slotless Design and FlexATX form factor.
By integrating the Ultra-AGP technology and advanced 128-bit graphic
display interface, SiS540 delivers high performance and up to 2 GB/s
memory bandwidth. Furthermore, SiS540 provides powerful slice layer
decoding DVD accelerator to improve the DVD playback performance. In
addition to providing the standard interface for CRT monitors, SiS540
also provides the Digital Flat Panel Port (DFP) for a standard
interface between a personal computer and a digital flat panel
monitor. To extend functionality and flexibility, SiS also provides
the "Video Bridge" (SiS301) to support the NTSC/PAL Video Output,
Digital LCD Monitor and Secondary CRT Monitor, which reduces the
external Panel Link transmitter and TV-Out encoder for cost effected
solution. SiS540 also adopts Share System Memory Architecture which
can flexibly utilize the frame buffer size up to 64MB.
The "Super-South Bridge" in SiS540 integrates all peripheral con-
trollers/accelerators/interfaces. SiS540 provides a total commun-
ication solution including 10/100Mb Fast Ethernet for Office
requirement. SiS540 offers AC’97 compliant interface that comprises
digital audio engine with 3D-hardware accelerator, on-chip sample rate
converter, and professional wavetable along with separate modem DMA
controller. SiS540 also provides interface to Low Pin Count (LPC)
operating at 33 MHz clock which is the same as PCI clock on the host,
and dual USB host controller with four USB ports that deliver better
connectivity and 2 x 12Mb bandwidth.
The built-in fast PCI IDE controller supports the ATA PIO/DMA, and the
Ultra DMA33/66 function that supports the data transfer rate up to 66
MB/s. It provides a separate data path for two IDE channels that can
eminently improve the performance under the multi-tasking environment.
***Configurations...
***Features:...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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