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**ET9000     "Jaguar" 486 Write Back Cache AT Single Chip       <Jun92
***Info:...
***Configurations:...
***Features:...
**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet]       ?...
**82C390SX   "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
**66x8       VIA clones [no datasheet]                               ?...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION

The  82489DX  Advanced   Programmable  Interrupt  Controller  provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.

The main  function of the  82489DX is to provide  interrupt management
across all  processors. This  dynamic interrupt  distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in  systems with multiple  I/O subsystems, where  each subsystem
can  have  its  own  set  of  interrupts.   This  chip  also  provides
inter-processor interrupts,  allowing any  processor to  interrupt any
processor or set  of processor. Each 82489DX I/O  init interrupt input
pin is individually  programmable by software as either  edge or level
triggered.  The interrupt vector and interrupt steering information an
be specified  per pin.  A  32-bit wide timer  is provided that  can be
programmed to interrupt the local processor.  the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate  time slice interrupts locally to  that processor.  the
82489DX   provides   32-bit   software    access   to   its   internal
registers. Since no  82489DX register read have any  side effects, the
82489DX registers  can be aliased  to a  user read-only page  for fast
user access (e.g., performance monitoring timers).

The 82489DX  supports a generalized naming/addressing  scheme that can
be tailored by  software to fit a variety of  system architectures and
usage  models.   It  also  supports 8259A  compatibility  by  becoming
virtually  transparent with  regard to  an externally  connected 8259A
style controller, making the 8259A visible to software.

***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92
***Notes:...
***Info:

The HTK340  chip set is  a two chip, high  performance, cost-effective
solution for the  80486SX DX, and DX2 processing  environments. In its
minimum configuration,  this highly integrated chip  set requires only
four external  TTL devices to  implement a fully compatible  IBM PC/AT
system at speeds up to 33MHZ.

The  HTK340  is based  upon  Headland's  HTK320  Bus Architecture  and
consists of the HT321-ISA  Bus Controller and the HT342-Memory Control
Unit  (MCU). Both  chips are  packaged in  184 pin  plastic  quad flat
packs.

The  HTK340 is unique  in that  it provides  performance approximating
that  of   large  secondary  cache  systems,   including  the  highest
performance  write  back  cache  architectures, without  any  external
cache. Secondary cache solutions  should be considered in applications
that make use of multi-tasking  and large model operating systems. The
Headland  HT44 secondary  cache  was  designed to  meet  the cost  and
performance objectives for these  applications.  The key to this level
of performance is  the 4-level deep write buffer,  which includes byte
gathering for up to 32-bit DRAM writes.

Due to  the effectiveness of the  primary cache internal  to the 80486
most of the bus activity in a PC/AT compatible environment consists of
writes.  Indeed, this  write activity  consists almost  exclusively of
writes of either  bytes or Words (16 bit  entities). In addition, much
of this write  activity is into sequential memory  locations. The byte
gathering feature of the buffer  has the effect of reducing the number
of memory accesses required. Since the 80486 can always write into the
buffer with  zero wait states (assuming  the buffer is  not full), and
the  buffer can  empty faster  than it  can be  filled for  most write
activity, the net effect is that the writes from the CPU never cause a
wait state.

The HTK340 can  support Peripheral Devices such as VGA  or SCSI on the
local processor  bus, or any other  devices that are  designed to work
within  the 80486  bus protocol  and  timing. By  eliminating the  ISA
backplane  bottleneck,  system   designers  can  greatly  improve  the
performance of functions such as graphics generation and disk access.

The  HTK340  supports up  to  4 banks  of  DRAM,  configurable as  1-4
banks. This  flexible memory architecture allows for  any memory type,
from 256K to 16M devices,  in any bank.  Maximum system performance is
achieved  from  the  DRAM   banks  through  various  means,  including
interleaving  of  memory  banks  and/or  paging, and  CAS  before  RAS
refresh. The memory can also be tuned to maximum potential through the
use  of  extensive  DRAM  timing control  registers.   These  controls
include: precharge time, access time  on reads, active time on writes,
as well  as CAS and RAS  delays.  In addition,  further system perfor-
mance is  gained by separate timing  parameters on the  read and write
cycles which allow  system designers to take maximum  advantage of the
pipelined structure of the chip set.

The  HTK340 also  supports  extensive mapping  registers, which  allow
system designers to take maximum  advantage of system memory. The chip
set  supports Shadow/Remap  in  16K  blocks between  the  640K and  1M
boundaries, and eliminates the requirement for external decoding logic
by supporting  26 programmable  non-cache regions. Devices  which meet
HTK340  local bus  requirements  may be  implemented without  external
TTL. The mapping  structure of the HTK340 provides  for a single 8-bit
EPROM to be used for both  the System and Video BIOS, further reducing
system chip count and cost.

***Configurations:...
***Features:...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...