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**EFAR-8290WB 386/486 Writeback PC/AT Chipset     [no datasheet]     ?
***Notes:...
***Info:
82EC495 System Controller (SYSC)

SYSC  monitors two  reset  sources, RSTl##  and  RST2#, and  generates
CPURST and  NPRST signals to  CPU and coprocessor,  respectively.  The
SYSC Controller contains Burst Line Fill Control Logic. The controller
provides 2 DMA Upper Address Latches, Page Mode DRAM Controller, Clock
Generation  for CPU  Processor  and AT-Bus,  two Noncacheable  Address
Comparators,  CPU  Interface   Control,  Integrated  Write-back  Cache
Controller with Built-in Tag  Comparator, Decoupling Refresh for Local
DRAM and AT-Bus Memory.

82EC392 Data Buffer Controller (DBC)

The 82EC392  performs all of  the data buffering functions.  Under the
control  of the processor,  the 82EC392  routes data  to and  form the
local CPU Bus.

The DBC performs Data Bus Conversion  when CPU accesses to 16 or 8 bit
device  through 32/16  bit instruction.   The bus  conversion  is also
supported for DMA/Master cycle for  the transfer between local DRAM or
cache memory and devices which resides on AT bus.

Parity Generation/Detection Logic will  compare the parity bit and the
parity generated from the data byte. If a mismatch happens, the parity
error will be generated.

In  order to  reduce  the  components count,  DBC  provides the  clock
sources for the timer of 8OC206 and 8042 Keyboard Controller.

The DBC  also monitors both  the PWGDS# (Powergood) signal  from power
supply and reset  signal from the reset switch.   The DBC provides the
Numeric Coprocessor  support for 387 and 3167  without external logic
components.

In addition, the DBC provides  Chip Select for Keyboard Controller and
RTC, Keyboard Reset and  Gate A20Emulation Logic, Speaker Control, and
NMI Logic.

***Configurations:...
**82EC798     386/486 Writeback PC/AT Single Chip [no datasheet]     ?
**Other:...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
**IBM AT: MC146818 Real Time Clock                                 <84
***Info:...
***Versions:...
***Features:
o   Low-Power, High-Speed, High-Density CMOS
o   Internal Time Base and Oscillator
o   Counts Seconds, Minutes, and Hours of the Day
o   Counts Days of the Week, Date, Month, and Year
o   3 V to 6 V Operation
o   Time Base Input Options: 4.194304 MHz, 1.048576 MHz, or 32,768 kHz
o   Time Base Oscillator for Parallel Resonant Crystals
o   40 to 200 uW Typical Operating Power at Low Frequency Time Base
o   4.0 to 20 mW Typical Operating Power at High Frequency Time Base
o   Binary or BCD Representation of Time, Calendar, and Alarm
o   12- or 24-Hour Clock with AM and PM in 12-Hour Mode
o   Daylight Savings Time Option
o   Automatic End of Month Recognition
o   Automatic Leap Year Compensation
o   Microprocessor Bus Compatible [this means absolutely nothing]
o   MOTEL Circuit for Bus Univerality
o   Multiplexed Bus for Pin Efficiency
o   Interfaced with Software as 64 RAM Locations
o   14 Bytes of Clock and Control Registers
o   50 Bytes of General Purpose RAM
o   Status Bit Indicates Data Integrity
o   Bus Compatible Interrupt Signals (IRQ)
o   Three Interrupts are Separately Software Maskable and Testable
      Time-of-Day Alarm, Once-per-Second to Once-per-Day
      Periodic Rates from 30.5 us to 500 ms
      End-of-Clock Update Cycle
o   Programmable Square-Wave Output Signal
o   Clock Output May Be Used as Microprocessor Clock Input
      At Time Base Frequency /1 or /4
o   24-Pin Dual-In-Line Package



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