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**EFAR-8290WB 386/486 Writeback PC/AT Chipset [no datasheet] ?
***Notes:...
***Info:
82EC495 System Controller (SYSC)
SYSC monitors two reset sources, RSTl## and RST2#, and generates
CPURST and NPRST signals to CPU and coprocessor, respectively. The
SYSC Controller contains Burst Line Fill Control Logic. The controller
provides 2 DMA Upper Address Latches, Page Mode DRAM Controller, Clock
Generation for CPU Processor and AT-Bus, two Noncacheable Address
Comparators, CPU Interface Control, Integrated Write-back Cache
Controller with Built-in Tag Comparator, Decoupling Refresh for Local
DRAM and AT-Bus Memory.
82EC392 Data Buffer Controller (DBC)
The 82EC392 performs all of the data buffering functions. Under the
control of the processor, the 82EC392 routes data to and form the
local CPU Bus.
The DBC performs Data Bus Conversion when CPU accesses to 16 or 8 bit
device through 32/16 bit instruction. The bus conversion is also
supported for DMA/Master cycle for the transfer between local DRAM or
cache memory and devices which resides on AT bus.
Parity Generation/Detection Logic will compare the parity bit and the
parity generated from the data byte. If a mismatch happens, the parity
error will be generated.
In order to reduce the components count, DBC provides the clock
sources for the timer of 8OC206 and 8042 Keyboard Controller.
The DBC also monitors both the PWGDS# (Powergood) signal from power
supply and reset signal from the reset switch. The DBC provides the
Numeric Coprocessor support for 387 and 3167 without external logic
components.
In addition, the DBC provides Chip Select for Keyboard Controller and
RTC, Keyboard Reset and Gate A20Emulation Logic, Speaker Control, and
NMI Logic.
***Configurations:...
**82EC798 386/486 Writeback PC/AT Single Chip [no datasheet] ?
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**IBM AT: MC146818 Real Time Clock <84
***Info:
The MC146818 Real-Time Clock plus RAM is a peripheral device which
includes the unique MOTEL concept for use with various
microprocessors, microcomputers, and larger computers. This part
combines three unique features: a complete time-of-day clock with
alarm and one hundred year calender, a programmable periodic interrupt
and square-wave generator, and 50 bytes of low-power static RAM. The
MC146818 uses high-speed CMOS technology to interface with 1 MHz
processor busses, while consuming very little power.
The Real-Time Clock plus RAM has two distinct uses. First, it is
designed as a battery powered CMOS part (in an otherwise NMOS/TTL
system) including all the common battery backed-up functions such as
RAM, time, and calendar. Secondly, the MC146818 may be used with a
CMOS microprocessor to relieve the software of the timekeeping
workload and to extend the available RAM of an MPU such as the
MC146805E2
***Versions:...
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