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**Who made the first chip set?
By the criteria of (2.) in 'Definition of a chip set' many sources
state this to be the Chips and Technologies NEAT chip set. I don't
know why this is stated as it is most definitely incorrect. The CS8221
NEW Enhanced AT (NEAT) chip set consisting of the chips;
82C211/82C212/82C215/82C206 was as far as I can establish, first
released sometime in 1986.
C&T itself have an earlier chip set called the CS8220 PC/AT compatible
Chip Set, and consists of the following chips; 82C201/82C202/
82A203/82A204/82A205. It was first available in OCT-85. (see:C&T>
CS8220>Notes for further info.)
That is, AFAIK, the first motherboard chip set from C&T and AFAIK the
worlds first chip set that meets the criteria of (2.). However C&T did
already have on the market their popular EGA chip set, but that isn't
a motherboard chip set.
By the criteria of (1.), IBM, or Intel, see IBM>PC/XT chip set.
Another pre-'86 chipset is the Faraday FE2010. The datasheet includes
a schematic on the very last page dated 11/22/85. This only indicates
the chip set was on paper at that date. An acutal release date has not
been found.
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
**EFAR-8290WB 386/486 Writeback PC/AT Chipset [no datasheet] ?
***Notes:...
***Info:
82EC495 System Controller (SYSC)
SYSC monitors two reset sources, RSTl## and RST2#, and generates
CPURST and NPRST signals to CPU and coprocessor, respectively. The
SYSC Controller contains Burst Line Fill Control Logic. The controller
provides 2 DMA Upper Address Latches, Page Mode DRAM Controller, Clock
Generation for CPU Processor and AT-Bus, two Noncacheable Address
Comparators, CPU Interface Control, Integrated Write-back Cache
Controller with Built-in Tag Comparator, Decoupling Refresh for Local
DRAM and AT-Bus Memory.
82EC392 Data Buffer Controller (DBC)
The 82EC392 performs all of the data buffering functions. Under the
control of the processor, the 82EC392 routes data to and form the
local CPU Bus.
The DBC performs Data Bus Conversion when CPU accesses to 16 or 8 bit
device through 32/16 bit instruction. The bus conversion is also
supported for DMA/Master cycle for the transfer between local DRAM or
cache memory and devices which resides on AT bus.
Parity Generation/Detection Logic will compare the parity bit and the
parity generated from the data byte. If a mismatch happens, the parity
error will be generated.
In order to reduce the components count, DBC provides the clock
sources for the timer of 8OC206 and 8042 Keyboard Controller.
The DBC also monitors both the PWGDS# (Powergood) signal from power
supply and reset signal from the reset switch. The DBC provides the
Numeric Coprocessor support for 387 and 3167 without external logic
components.
In addition, the DBC provides Chip Select for Keyboard Controller and
RTC, Keyboard Reset and Gate A20Emulation Logic, Speaker Control, and
NMI Logic.
***Configurations:...
**82EC798 386/486 Writeback PC/AT Single Chip [no datasheet] ?
**Other:...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01
Chips:
[82845] (MCH) [82801BA] (ICH2)
CPUs: Celeron, Pentium 4
DRAM Types: DDR 200/266 or PC133
Mem Rows: --
DRAM Density: 64Mbit 128Mbit 256Mbit
Max Mem: 2GB DDR/ 3GB DSRAM
ECC/Parity: ECC
AGP speed: 1x 2x 4x
Bus Speed: 400 MT/s (100 MHz QDR)
PCI Clock/Bus: 1/3 PCI 2.2
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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