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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**82C712   Universal Peripheral Controller II                  c:Jan91
***Info:...
***Versions:...
***Features:
o   For ADAPTER Applications with configuration via hardware (Jumper 
    selectable)
o   Low Power CMOS, 100 pin PQFP Package
o   100% IBM PC-XT/AT Compatibility.
o   24 mA IBM AT/XT Bus Interface Buffers
o   Schmitt Trigger Input on Reset Pin and FDC interface inputs
o   Two 16450 Compatible UARTs
o   1 IBM PC-XT/AT Compatible Enhanced (Bi-Directional) Parallel 
    Port 
o   Game Port Chip Select (GPCS)
o   24 mA Parallel Port Output Drivers
o   Single 24 MHz Crystal/Oscillator for UART and Floppy Disk 
    Controller
o   Fully uPD72065B and IBM-BIOS Compatible Floppy Disk Controller
    - Licensed NEC design
    - 48 mA floppy drive interface buffers
    - Data rate and drive control registers
    - Two pin programmable precompensation modes
    - Supports two floppy drives directly and up to four with an 
      external decoder
    - DMA enable logic
o   On-Chip Precision Analog Data Separator
    - +/-380ns at 500K bps
    - +/-740ns at 250K bps
    - Automatically selects one of three filters
    - Supports 250 Kb/s, 300 Kb/s, 500 Kb/s & 1 Mb/s data rates 

**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:
o   50 MHz Intel486 DX CPU 
    - RISC Integer Core with Frequent Instructions Executing in One 
      Clock
    - 160 Mbyte/Sec Burst Bus
    - 41 Dhrystone MIPs
    - 11.5M Double Precision Whetstones/Sec.
    - On-Chip Cache and FPU
o   Highly Flexible
    - Supports 128 Kbyte and 256 Kbyte Configurations
    - Complete MESI Protocol Support
    - 32- or 64-Bit Memory Bus Width
    - Synchronous, Asynchronous, and Strobed Memory Bus Protocols
    - Variable Cache Line Sizes and Sectoring
    - Cache Data Parity Option
o   High Performance Second Level Cache
    - Two-Way Set Associative
    - Write-Back or Write Through Cache
    - Zero Wait State Cache Access
    - Concurrent CPU Bus, Memory Bus, and Internal Array Operation
o   Full Multiprocessing Support
    - Implements MESI Write-Back Cache Protocol
    - Low Bus Utilization
    - Automatically Maintains 1st Level Cache Consistency
    - Supports Read-for-Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HTK320        386DX Chip Set                                 c:Sep91
***Info:...
***Configurations:...
***Features:...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
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