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**82C710 Universal Peripheral Controller c:Aug90
***Info:
The 82C710 Universal Peripheral Controller (UPC) is a single chip
controller offering the complete I/P solution for the PC-XT & PC-AT
environments. The chip is an LSI implementation of the most commonly
used peripheral devices found in an IBM PC, XT or AT. It features 24
mA drivers for the output buffers, including the host data bus and
parallel port data bus. it incorporates one 16450 compatible UART, one
enhanced parallel port (with bi-directional capability), an IDE
compatible hard disk interface, a uPD72065B compatible floppy disk
controller, PS/2 type mouse logic, and various chip selects. Decoding
logic and support for main, auxiliary and standby power supplies and
software configurable base addresses for these devices, operational
modes and interrupts are also included. Power management aspects of
the 82C710 includes modular power down for each port, and software
oscillator disable. The hardware power management is done through the
PWRGD pin. When the chip is powered down (i.e. when PWRGD is inactive)
the current drawn is less than 250 microAmps, all the inputs are
disabled, and all outputs are tristated. The contents of all the
registers are preserved, as long as power supply to the 82C710 is
maintained.
The host interface is a PC compatible, (i.e. D0-D7, A0,A9, IOR, IOW,
AEN, MINTR, FINTR, PINTR, SINTR, and RESET), and can be connected
directly to the bus. The data buffers (D0-D7, PD0-PD7, IDED7) are
capable of sinking 24 mA @ 0.5V, the parallel port control signals are
open collector with internal pull up, and are capable of sinking 24 mA
@ 0.5V.
The UART implements a fully functional serial link. Programmable
character length, parity generation and detection, stop-bit generation
and baud rate generation are provided. Double buffering is used so
that precise synchronization is unnecessary. Status information is
accessible to the CPU by reading internal registers. MODEM control
lines are provided, as are internal diagnostic functionality and
interrupt prioritization. Support for an auxiliary power system (such
as that derived from a telephone line or R8232 link) permits a UPC in
a battery-powered device to consume no battery power until an incoming
character is detected.
The parallel port can be configured for output only (printer
application) or input and output (scanner application). The necessary
control signals are provided for use as a Centronics-compatible
(output only) parallel port. For scanner applications, a Cent-
ronics-like interface is used. Such an interface is utilized by the
RICOH 1830 scanner.
The configuration RAM and circuitry support programmable base
addresses for all registers internal to the UPC. This permits creation
of a menu-driven program for system configuration. Selection of
sources for interrupts, enabling and configuring of on-chip subsystems
(UARTs, parallel port, etc.) and control of the configuration process
itself are also handled with this RAM and its associated circuitry.
The remainder of this data sheet will consider each of the aforesaid
subsystems individually. Sections containing more general design data
for the chip as a whole are at the end along with electrical and
physical characteristics.
***Versions:...
***Features:...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*OPTi...
**82C898 System/Power Management Controller (non-cache)c:Nov94
***Notes:...
***Info:
Overview
The 82C898 provides a highly integrated solution for fully compatible,
high performance PC/AT platforms. The 82C898 supports 486SX/DX/DX2/DX4
and P24T microprocessors in the most cost effective and power
efficient designs available today. For high-end system applications,
this device offers optimum performance for systems running up to
50MHz.
Based fundamentally on OPTi’s proven 82C801 and 82C802 design
architectures, the 82C898 adds additional memory configurations and
extensive power management control for the processor and other
motherboard components.
The 82C898 supports the latest in write-back processor designs from
Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA local
bus for compatibility and performance. It also includes an 82C206
Integrated Peripherals Controller (IPC), all in a single 208-pin PQFP
(Plastic Quad Flat Pack) for low cost.
Power Management
Figure 2-1 [see datasheet] exemplifies the flexibility of an
82C898/82C602-based designs GREEN strategy. System designs can easily
accommodate both SLe and non-SLe CPUs. If an Intel non-SLe CPU is
used, SMI#, SMIAOT#, and FLUSH# are no connects. One design can easily
accommodate both types of processors with minimal changes for
upgrades.
***Configurations:...
***Features:...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
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