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**82C710 Universal Peripheral Controller c:Aug90
***Info:
The 82C710 Universal Peripheral Controller (UPC) is a single chip
controller offering the complete I/P solution for the PC-XT & PC-AT
environments. The chip is an LSI implementation of the most commonly
used peripheral devices found in an IBM PC, XT or AT. It features 24
mA drivers for the output buffers, including the host data bus and
parallel port data bus. it incorporates one 16450 compatible UART, one
enhanced parallel port (with bi-directional capability), an IDE
compatible hard disk interface, a uPD72065B compatible floppy disk
controller, PS/2 type mouse logic, and various chip selects. Decoding
logic and support for main, auxiliary and standby power supplies and
software configurable base addresses for these devices, operational
modes and interrupts are also included. Power management aspects of
the 82C710 includes modular power down for each port, and software
oscillator disable. The hardware power management is done through the
PWRGD pin. When the chip is powered down (i.e. when PWRGD is inactive)
the current drawn is less than 250 microAmps, all the inputs are
disabled, and all outputs are tristated. The contents of all the
registers are preserved, as long as power supply to the 82C710 is
maintained.
The host interface is a PC compatible, (i.e. D0-D7, A0,A9, IOR, IOW,
AEN, MINTR, FINTR, PINTR, SINTR, and RESET), and can be connected
directly to the bus. The data buffers (D0-D7, PD0-PD7, IDED7) are
capable of sinking 24 mA @ 0.5V, the parallel port control signals are
open collector with internal pull up, and are capable of sinking 24 mA
@ 0.5V.
The UART implements a fully functional serial link. Programmable
character length, parity generation and detection, stop-bit generation
and baud rate generation are provided. Double buffering is used so
that precise synchronization is unnecessary. Status information is
accessible to the CPU by reading internal registers. MODEM control
lines are provided, as are internal diagnostic functionality and
interrupt prioritization. Support for an auxiliary power system (such
as that derived from a telephone line or R8232 link) permits a UPC in
a battery-powered device to consume no battery power until an incoming
character is detected.
The parallel port can be configured for output only (printer
application) or input and output (scanner application). The necessary
control signals are provided for use as a Centronics-compatible
(output only) parallel port. For scanner applications, a Cent-
ronics-like interface is used. Such an interface is utilized by the
RICOH 1830 scanner.
The configuration RAM and circuitry support programmable base
addresses for all registers internal to the UPC. This permits creation
of a menu-driven program for system configuration. Selection of
sources for interrupts, enabling and configuring of on-chip subsystems
(UARTs, parallel port, etc.) and control of the configuration process
itself are also handled with this RAM and its associated circuitry.
The remainder of this data sheet will consider each of the aforesaid
subsystems individually. Sections containing more general design data
for the chip as a whole are at the end along with electrical and
physical characteristics.
***Versions:...
***Features:...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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**IBM AT: MC146818 Real Time Clock <84
***Info:...
***Versions:...
***Features:
o Low-Power, High-Speed, High-Density CMOS
o Internal Time Base and Oscillator
o Counts Seconds, Minutes, and Hours of the Day
o Counts Days of the Week, Date, Month, and Year
o 3 V to 6 V Operation
o Time Base Input Options: 4.194304 MHz, 1.048576 MHz, or 32,768 kHz
o Time Base Oscillator for Parallel Resonant Crystals
o 40 to 200 uW Typical Operating Power at Low Frequency Time Base
o 4.0 to 20 mW Typical Operating Power at High Frequency Time Base
o Binary or BCD Representation of Time, Calendar, and Alarm
o 12- or 24-Hour Clock with AM and PM in 12-Hour Mode
o Daylight Savings Time Option
o Automatic End of Month Recognition
o Automatic Leap Year Compensation
o Microprocessor Bus Compatible [this means absolutely nothing]
o MOTEL Circuit for Bus Univerality
o Multiplexed Bus for Pin Efficiency
o Interfaced with Software as 64 RAM Locations
o 14 Bytes of Clock and Control Registers
o 50 Bytes of General Purpose RAM
o Status Bit Indicates Data Integrity
o Bus Compatible Interrupt Signals (IRQ)
o Three Interrupts are Separately Software Maskable and Testable
Time-of-Day Alarm, Once-per-Second to Once-per-Day
Periodic Rates from 30.5 us to 500 ms
End-of-Clock Update Cycle
o Programmable Square-Wave Output Signal
o Clock Output May Be Used as Microprocessor Clock Input
At Time Base Frequency /1 or /4
o 24-Pin Dual-In-Line Package
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