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**CS8221 NEW Enhanced AT (NEAT) (82C211/82C212/82C215/82C206) c86
***Info:
The CS8221 PC/AT compatible NEAT CHIPSet is an enhanced, high
performance 4 chip VLSI implementation (including the 82C206 IPC) of
the control logic used on the IBM Personal Computer AT. The flexible
architecture of the NEAT CHIPSet allows it to be used in any 80286
based system.
The CS8221 NEAT CHIPSet provides a complete 286 PC/AT compatible
system, requiring only 24 logic components plus memory devices.
The CS8221 NEAT CHIPSet consists of the 82C211 CPU/Bus controller, the
82C212 Page/interleave and EMS Memory controller. the 82C215
Data/Address buffer and the 82C206 Integrated Peripherals Controller
(IPC).
The NEAT CHIPSet supports the local CPU bus, a 16 bit system memory
bus, and the AT buses as shown in the NEAT System Block Diagram [see
datasheet]. The 82C211 provides synchronization and control signals
for all buses. The 82C211 also provides an independent AT bus clock
and allows for dynamic selection between the processor clock and the
user selectable AT bus clock. Command delays and wait states are
software configurable, providing flexibility for slow or fast peri-
pheral boards.
The 82C212 Page/interleave and EMS Memory controller provides an
interleaved memory sub-system design with page mode operation. It
supports up to 8 MB of on-board DRAM with combinations of 64Kbit,
256Kbit and 1Mbit DRAMs. The processor can operate at 16MHz with
0.5-0.7 wait state memory accesses, using 100 nsec DRAMs. This is
possible through the Page Interleaved memory scheme. The Shadow RAM
feature allows taster execution of code stored in EPROM, by down
loading code from EPROM to RAM. The RAM then shadows the EPROM for
further code execution. In a DOS environment, memory above 1Mb can be
treated as LIM EMS memory.
The 82C215 Data/Address buffer provides the buffering and latching
between the local CPU address bus and the Peripheral address bus. It
also provides buffering between the local CPU data bus and the memory
data bus. The parity bit generation and error detection logic resides
in the 82C215.
The 82C206 Integrated Peripherals Controller is an integral part of
the NEAT CHIPSet. It is described in the 82C206 Integrated Peri-
pherals Controller data book.
System Overview
The CS8221 NEAT CHIPSet is designed for use in 12 to 16 MHz 80286
based systems and provides complete support for the IBM PC/AT
bus. There are four buses supported by the CS8221 NEAT CHIPSet as
shown in Figure 1 [see datasheet]: CPU local bus (A and D), system
memory bus (MA and MD), I/O channel bus (SA and SD), and X bus (XA and
XD). The system memory bus is used to interface the CPU to the DRAMs
and EPROMs controlled by the 82C212. The I/O channel bus refers to
the bus supporting the AT bus adapters which could be either 8 bit or
16 bit devices. The X bus refers to the peripheral bus to which the
82C206 IPC and other peripherals are attached in an IBM PC/AT.
***Configurations:...
***Features:...
**CS8223 LeAPset [no datasheet] ?
**CS8225 CHIPS/250 PS/2 50/60 [no datasheet, some info] c88...
**CS8227 CHIPSlite (82C235/82C641) ?...
**CS8230 386/AT (82C301/302/303/304/305/306)cFeb87...
**CS8231 TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306) c86...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95
***Info:
The CS4041 is the first product in the GreenCHIPS CHIPSet product
portfolio of Chips and Technologies, Inc. It provides all of the
system logic for implementing a high performance, Energy Star
compliant 486 PC/AT design, while maintaining an extremely competitive
cost structure. The powerful feature set includes the CHIPS "standard"
system blocks and offers a new level of system integration while
addressing the ever evolving requirements that the market place
demands. It is 100% PC/AT compatible and directly supports the 486DX,
486DX2, 486DX4, 486SX and 486 derivatives that support the CPU write
back cache architecture.
The high performance CHIPSet consists of the F84041 Systems Controller
and F84045 GreenCHIPS IPC. The F84041 System Controller is packaged in
a 208-pin PQFP and integrates the major system logic
functions. Included in the F84041 is the CHIPS patented Page
Interleave DRAM controller, high performance cache controller, VL
local bus controller, ISA bus controller, power management module, a
local bus IDE controller and fully compatible 8042 keyboard controller
with PS/2 mouse support. The companion F84045 is packaged in a 100 pin
PQFP and contains the industry standard Integrated Peripheral
Controller (IPC) which includes the DMA controllers, timers, interrupt
controllers and real time clock.
The enhanced feature set of GreenCHIPS DRAM and cache controllers are
perfect for today's High Performance PC/AT designs. The page
interleave DRAM controller offers high performance as well as extreme
flexibility in supporting 486 memory subsystems. The DRAM controller
supports up to eight banks of memory that can be configured with 256K,
1M, 4M or 16M memory devices. Page interleaving, timing modes, memory
mix options, direct drive support and block by block parity support
can be tuned to meet the most optimum requirements for the system
design. In addition, the high performance secondary cache controller
provides options that can be optimized for performance, cost or
both. The direct mapped cache architecture employs internal
comparators with external TAG and data SRAM that can operate in a
write-through or write-back mode. Cache sizes from 64K to 1M are
supported with flexible single bank or dual bank support that allow
flexible timing mode selection based on CPU speed and SRAM speed.
The "Green" in GreenCHIPS comes from the Power management support
integrated in the CHIPSet. The CS4041 provides the perfect level of
power management support for Energy Star compliant desktops. Included
in the power management section is direct support for SMM operation
and clock switching for the popular 486 derivatives. Two event timers,
programmable I/O pins, I/O restart and programmable event detection
provide a wide range of options for power management selection and
customization.
The CS4041 provides new levels of integration in system logic CHIPSets
by providing a local bus IDE interface and keyboard controller. The
robust local bus IDE interface is decoupled from the AT state machine
and does not use a VL local bus load. The interface is versatile
enough to support up to eight IDE drives allowing each drive to have
unique command settings. The result is the best performance for each
drive type allowing significant performance gains over the standard
ISA interface. This is accomplished without any compromise to the
standard VL local bus.
CPUs Supported
oIntel 486 CPUs
oAMD 486 CPUs
oCyrix 486 CPUs
oIBM 486 CPUs
oL1 (CPU) write back cache fully supported
oSMI support (both Intel and Cyrix)
oClock Frequencies:
25MHz, 33MHz, 40MHz, 50MHz
***Configurations:...
***Features:...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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