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**CS8221 NEW Enhanced AT (NEAT) (82C211/82C212/82C215/82C206) c86
***Info:
The CS8221 PC/AT compatible NEAT CHIPSet is an enhanced, high
performance 4 chip VLSI implementation (including the 82C206 IPC) of
the control logic used on the IBM Personal Computer AT. The flexible
architecture of the NEAT CHIPSet allows it to be used in any 80286
based system.
The CS8221 NEAT CHIPSet provides a complete 286 PC/AT compatible
system, requiring only 24 logic components plus memory devices.
The CS8221 NEAT CHIPSet consists of the 82C211 CPU/Bus controller, the
82C212 Page/interleave and EMS Memory controller. the 82C215
Data/Address buffer and the 82C206 Integrated Peripherals Controller
(IPC).
The NEAT CHIPSet supports the local CPU bus, a 16 bit system memory
bus, and the AT buses as shown in the NEAT System Block Diagram [see
datasheet]. The 82C211 provides synchronization and control signals
for all buses. The 82C211 also provides an independent AT bus clock
and allows for dynamic selection between the processor clock and the
user selectable AT bus clock. Command delays and wait states are
software configurable, providing flexibility for slow or fast peri-
pheral boards.
The 82C212 Page/interleave and EMS Memory controller provides an
interleaved memory sub-system design with page mode operation. It
supports up to 8 MB of on-board DRAM with combinations of 64Kbit,
256Kbit and 1Mbit DRAMs. The processor can operate at 16MHz with
0.5-0.7 wait state memory accesses, using 100 nsec DRAMs. This is
possible through the Page Interleaved memory scheme. The Shadow RAM
feature allows taster execution of code stored in EPROM, by down
loading code from EPROM to RAM. The RAM then shadows the EPROM for
further code execution. In a DOS environment, memory above 1Mb can be
treated as LIM EMS memory.
The 82C215 Data/Address buffer provides the buffering and latching
between the local CPU address bus and the Peripheral address bus. It
also provides buffering between the local CPU data bus and the memory
data bus. The parity bit generation and error detection logic resides
in the 82C215.
The 82C206 Integrated Peripherals Controller is an integral part of
the NEAT CHIPSet. It is described in the 82C206 Integrated Peri-
pherals Controller data book.
System Overview
The CS8221 NEAT CHIPSet is designed for use in 12 to 16 MHz 80286
based systems and provides complete support for the IBM PC/AT
bus. There are four buses supported by the CS8221 NEAT CHIPSet as
shown in Figure 1 [see datasheet]: CPU local bus (A and D), system
memory bus (MA and MD), I/O channel bus (SA and SD), and X bus (XA and
XD). The system memory bus is used to interface the CPU to the DRAMs
and EPROMs controlled by the 82C212. The I/O channel bus refers to
the bus supporting the AT bus adapters which could be either 8 bit or
16 bit devices. The X bus refers to the peripheral bus to which the
82C206 IPC and other peripherals are attached in an IBM PC/AT.
***Configurations:...
***Features:...
**CS8223 LeAPset [no datasheet] ?
**CS8225 CHIPS/250 PS/2 50/60 [no datasheet, some info] c88...
**CS8227 CHIPSlite (82C235/82C641) ?...
**CS8230 386/AT (82C301/302/303/304/305/306)cFeb87...
**CS8231 TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306) c86...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92
***Info:...
***Configurations:...
***Features:
Flexible Systems Logic
o Supports 486DX, 486SX, 386DX and Super386 CPUs
o Supports 487 and 4167 on 486 CPU mode and 367, 3167 on 386 CPU
mode
o Burst Mode support in cache and DRAM modes
o 64K, 128K, 256K, and 512K cache size
o Direct0mapped, write back operation, with pipeline allocate on
read miss
o 2-1-1-1 burst for cache reads to the 486 and 486SX
o interleaved data SRAMs
o 3-1-1-1 burst read with 486SX CPU at 16/20/25 MHz with no cache
o 256K, 1M and 4M deep DRAM support
o Support for 4Mx4 DRAMs with 12/10 or 11/11 addressing
o Page mode DRAM access with option of using page interleaving
o Up to 8 banks of 32-bit DRAMs
o Option for using asynchronous or synchronous AT clock
o Fast 12 MHz AT bus support
o Local bus master and slave support
o Programmable I/O chip select output signals
Designed for Cost Effective Windows Acceleration
o Workstation-like graphics performance achieved via the 64200
Wingine
Memory Bus Architecture
o Highly integrated design (non-multiplexed system bus, direct bus
drive, minimum external glue logic)
o Direct linear mapping of entire video memory anywhere in system
memory space
o Flexible video memory configurations
o supports high resolution display modes with 2MB VRAM
o Full VGA compatibility in 'VGA' mode
o Interfaces directly with the 82C481 True-Color Graphics
Accelerator
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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