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*Chips & Technologies...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89
***Info:
CHIPS/280 is a 7-device, enhanced CMOS implementation of most of the
system logic necessary to implement personal computers compatible to
IBM PS/2 Model 70/80. CHIPS/280 enables OEMs to offer compatible PS/2
models 70/80, that are more integrated and superior in performance
than IBM's Model 70/80.
CHIPS/280 includes the CS8238 System Logic CHIPSet, the 82C607
Multi-Function Controller with Analog Data Separator and 16550
compatible serial port, and the Enhanced Gate-Level Compatible
82C451/452 VGA chip as indicated in Figures 1a and lb [see data
sheet]. With these 7 VLSI devices, it requires only 59 additional
components plus memory to implement compatible PS/2 Models 70/80
superior to IBM's models.
CHIPS/280 is designed to maximize the performance of the 80386
microprocessor by coupling it to a high performance page/interleaved
memory sub-system. The maximum page size supported by the CHIPS/280
architecture is 16 KBytes when 1 Mbyte DRAMs are used (16 MB of
onboard Memory) and the four way interleaved mode of operation is
selected. When executing within a page, the DRAM memory sub-system can
execute at the same speed as the processor. To the 386, the mem- ory
sub-system appears as a 16 KByte direct mapped cache, using relatively
inexpensive DRAMs. When operating at 16, 20 or 25 MHZ, the average
waitstate incurred is less than 0.7. Additionally, by using Shadow RAM
techniques, the BIOS code can also be executed with near zero wait
states.
In addition to the high performance memory interface, CHIPS/280
supports a fast Matched Memory Cycle reducing the access time from 200
ns to 120 ns at 25 MHz. CHIPS proprietary Fast VGA cycle allows VGA
I/O accesses to be performed within 187.5 ns@ 16 MHz, 150 ns @ 20 MHz,
and 120 ns @ 25 MHz.
Regardless of the CPU speed, the DMA controller operates at 10
MHz. Once the DMA and the peripherals are tuned, for example, with a
1:1 interleaving on the Hard Disk, CHIPS/280 continues to deliver
dependable high performance.
***Configurations:...
***Features:...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C546/547 Python PTM3V c:94
***Notes:...
***Info:
The OPTi Python Chipset provides a highly integrated solution for
fully compatible, high-performance PC/AT platforms. Together, with
OPTi's 82C206 Integrated Peripheral Controller (IPC), this chipset
will support the Pentium processor in the most cost effective and
feature-rich designs available today. This highly integrated approach
provides the foundation for a cost effective platform without
compromising performance. The OPTi Python Chipset supplies a powerful
solution positioned to deliver value without neglecting quality,
compatibility, or reliability.
The Python Chipset is comprised of two chips, the 82C547 System
Controller (SYSC) and the 82C546 AT Bus Controller (ATC). A complete
Pentium processor solution consists of the Python Chipset and the
82C206 Integrated Peripheral Controller (IPC).
82C546 (ATC) AT Bus Controller
The 82C546 ATC integrates the AT bus interface and data buffers for
transfers between the CPU data bus, local data bus and the DRAM data
bus. It also provides the ISA to local bus command translation.
o 208-pin PQFP
o Data bus buffer (host data to memory data)
o Data bus buffer control (ISA to memory)
o Parity generation and detection circuitry
o Keyboard controller chip select
o Local bus interface (ISA to local bus command translation)
82C547 (SYSC) System Controller
The 82C547 SYSC provides the control functions for the host CPU
interface, the 32-bit local bus interface, the 64-bit Level 2 (12)
cache and the 64-bit DRAM bus. The SYSC also controls the data flow
between the CPU bus, the DRAM bus, the local bus, and the 8/16-bit ISA
bus.
o 160-pin PQFP
o Pentium CPU interface
o DRAM controller
o L2 cache controller
o Ll cache controller
o Local bus interface
o Reset generation
o Arbitration logic
o Data bus buffer control (memory data to/from host data)
o Extended DMA page register
o Keyboard emulation of A20M# and CPU warm reset
o Port B and Port 92h Register
82C206 (IPC) Integrated Peripherals Controller
The 82C206 IPC provides two DMA controllers, two interrupt control-
lers, one timer/counter, and a real-time clock in an industry standard
single-chip solution for the peripherals attached to the PC/AT
peripheral bus.
o 84-pin PLCC or 100-pin PQFP
o Supports four DMA transfer modes
o Special Commands provided for ease of programming
Support Chips
The 82C606A and 82C606B are two buffer/translation devices used to
translate 3.3V signals to 5.0V signal levels in Python motherboard
solutions. These devices buffer the CPU address bus to the ISA and VL
address buses, the 82C546 ATC's memory data bus to the ISA data bus,
the peripheral XD bus to the ISA SA and SD buses. The 82C606A and
82C606B integrate a number of glue logic TTL devices (approximately
eleven), hence reducing the amount of TTL on the motherboard. The
82C606A and 82C606B devices are actually the same device with two
strapping options. Pulling the CONFI/2# pin high causes the device to
function in the 82C606A Mode. Pulling the CONFII2# pin low configures
the device to function in the 82C606B Mode of operation.
o 100-pin PQFP
o Mixed voltage to support 3.3V to 5.0V signal translation
o Two devices replace approximately eleven TTL devices
***Configurations:...
***Features:...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
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