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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Wait States at 66 MHz 
    - Two-Way Set Associative 
    - Writeback with MESI Protocol 
    - Concurrent CPU Bus and Memory Bus Operation 
    - Boundary Scan
o   Pentium Processor (735\90, 815\100)
    - Chip Set Version of Pentium Processor (735\90, 815\100) 
    - Superscalar Architecture
    - Enhanced Floating Point 
    - On-Chip 8K Code and 8K Data Caches
    - See Pentium Processor Family Data Book for More Information
o   Highly Flexible
    - 1 Mbyte to 2 Mbyte
    - 64-, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers and Burst Orders
o   Full Multiprocessing Support
    - Concurrent CPU, Memory Bus and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read For Ownership, Write-Allocation and Cache-to-Cache
      Transfers


**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98...
***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**W86C452   I/O controller for IBM PC/AT                         Jul89
***Info:
GENERAL DESCRIPTION

The W86C452 is an enhanced dual-channel version of the popular W86C450
asynchronous  communication element  (ACE) fabricated  using WINBOND'S
CMOS process.  It is  equivalent to VL160452  of the  VLSI Technology
Inc.

The  device   supports  two  serial-to-parallel   conversion  on  data
characters  received  from  a  peripheral  device  or  a  MODEM.   and
parallel-to-serial  conversion on  data characters  received  from the
CPU.

The CPU  can read the complete status  of the UART at  any time during
the  functional operation.  Status  information reported  includes the
type and condition  of the transfer operations being  performed by the
UART as  well as  any error conditions  (parity. overrun,  framing, or
break interrupt).

The UART includes  a programmable baud rate generator  that is capable
of dividing the timing reference clock input by divisors of l to (2^16
-1), and  producing a 16 x  clock for driving  the internal transmiter
logic. Provisions  are also included to  use this 16 x  clock to drive
the  receiver  logic.   The  UART includes  a  complete  MODEM-control
capability  and  a  processor-interrupt  system.   Interrupts  can  be
programmed  to  the  user’s  requirements,  minimizing  the  computing
required to handle the communications link.

In addition  to its communication interface  capabilities, the W86C452
provides the user with  a fully bidirectional parallel Centronics type
printer.  This part  allows  information received  from either  serial
communication port to be printed from the dual ACE.

***Versions:...
***Features:...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
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