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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98...
***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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*Winbond...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89
***Info:
GENERAL DESCRIPTION

The W860451 is an enhanced version of the popular W860450 asynchronous
communication element  (ACE) fabricated using  WINBOND'S CMOS process.
The  device   supports  one  serial-to-parallel   conversion  on  data
characters  received  from  a  peripheral  device  or  a  MODEM.   and
parallel-to-serial  conversion on  data characters  received  from the
CPU. The  CPU can  read the complete  status of  the UART at  any time
during the functional  operation. Status information reported includes
the type and  condition of the transfer operations  being performed by
the UART as well as any error conditions (parity, overrun, framing. or
break  interrupt).   The  UART   includes  a  programmable  baud  rate
generator that is capable of dividing the timing reference clock input
by divisors of 1 to (2^16 -  1), and producing a 16x clock for driving
the internal  transmitter logic. Provisions  are also included  to use
this  16x clock  to drive  the receiver  logic.  The  UART  includes a
complete  MODEM-control capability  and a  processor-interrupt system.
interrupts can  be programmed  to the user’s  requirements, minimizing
the computing required to handle the communications link.  In addition
to its communication interface  capabilities, the W860451 provides the
user with a parallel Centronics type printer.
***Versions:...
***Features:...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
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