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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION
The 82489DX Advanced Programmable Interrupt Controller provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.
The main function of the 82489DX is to provide interrupt management
across all processors. This dynamic interrupt distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in systems with multiple I/O subsystems, where each subsystem
can have its own set of interrupts. This chip also provides
inter-processor interrupts, allowing any processor to interrupt any
processor or set of processor. Each 82489DX I/O init interrupt input
pin is individually programmable by software as either edge or level
triggered. The interrupt vector and interrupt steering information an
be specified per pin. A 32-bit wide timer is provided that can be
programmed to interrupt the local processor. the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate time slice interrupts locally to that processor. the
82489DX provides 32-bit software access to its internal
registers. Since no 82489DX register read have any side effects, the
82489DX registers can be aliased to a user read-only page for fast
user access (e.g., performance monitoring timers).
The 82489DX supports a generalized naming/addressing scheme that can
be tailored by software to fit a variety of system architectures and
usage models. It also supports 8259A compatibility by becoming
virtually transparent with regard to an externally connected 8259A
style controller, making the 8259A visible to software.
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96
***Notes:...
***Info:...
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***Features:...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
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**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
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**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
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**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
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**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89
***Info:
GENERAL DESCRIPTION
The W860450/P is an improved specification version of the W86C250A
Universal Asynchronous Receiver/Transmitter [UART). The improved
specifications ensure compatibility with the state-of-the-art
CPUs. Functionally, the W860450/P is equivalent to the INS8250A of the
National Semiconductor. The W86C450/P is fabricated using WINBONDâs
CMOS process. The W860450/P performs serial-to-parallel conversion on
data characters received from a peripheral device or a MODEM, and
parallel-to-serial conversion on data characters received from the
CPU. The CPU can read the complete status of the W860450/P at any time
during the functional operation. Status information reported includes
the type and condition operation. Status information reported
includes the type and condition of the transfer operations being
performed by the W860450/P, as well as any error conditions (parity,
overrun, framing, or break interrupt).
The W860450/P includes a programmable baud rate generator that is
capable of dividing the timing reference clock input by divisors of l
to (2^16 - 4), and producing 16x clock for driving the internal
transmitter logic. Provisions are also included to use this 16x clock
to capability and a processor-interrupt system. Interrupts can be
programmed to the user's requirements, minimizing the computing
required to handle the communications link.
***Versions:...
***Features:...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
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