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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*OPTi...
**82C496/7       DXBB PC/AT Chipset (Cached)                 <01/16/92
***Info:
The OPTi  82C497 is a Direct  Mapped Write Back  cache controller with
one level write buffer that is  an optional part of the DXBB (Building
Block) Chip  set.  The DXBB also  contains the 82C496  and the 82C206,
which form the  heart of the system.  The 82C497 is  added to the DXBB
chip set for cache based systems.

The OPTi  82C496 offers an  upgradable CPU module  base-board solution
for the 80386  or the 80486 PC/AT system. By  swapping the CPU module,
the  vendor can configure  the 82C496  driven base-board  into various
32-bit AT  systems - 386 or 486  CPU, with cache or  without cache and
rated at 16MHz- 50MHz.

For the Non-Cache systems, the CPU interfaces directly with the 82C496
and the local devices, like the local VGA controller or the local hard
disk adaptor.

For cache based systems the 82C497 (the cache controller) sits between
the CPU and  the 82C496 and the local devices.  All the high frequency
signals are isolated by the  82C497. This allows the base-board to run
at a fixed speed  (25 or 33MHz) - while the CPU  and the Cache can run
synchronously at any determined  rated speed. This provides a reliable
upgrade method for the CPU modules.

***Configurations:...
***Features:...
**82C498         DXWB PC/AT chipset [no datasheet]                   ?...
**82C499         DXSC DX System Controller                        c:93...
**82C546/547     Python PTM3V                                     c:94...
**82C556/7/8     Viper [no datasheet]                                ?...
**82C556/7/8N    Viper-N  Viper Notebook Chipset             <05/25/95...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*TI (Texas Instruments)...
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*Unresearched:...
*VIA...
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*Western Digital...
*Winbond...
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89
***Info:...
***Versions:...
***Features:
o   Easily interfaces to most popular microprocessors.
o   Adds or deletes standard asynchronous communication bit (start, 
    stop, and parity) to or from serial data stream.
o   Holding and shift registers eliminate the need for precise 
    synchronization between the CPU and the serial data.
o   Independently controlled transmit, receive, line status, and data 
    set interrupts.
o   Programmable baud generator allow division of any input clock by 1 
    to (2^16 - 1) and generates the internal 16x clock.
o   Independent receiver clock input.
o   MODEM control functions (CTS, RTS. DSR, DTR, RI, and DCD).
o   Fully programmable serial-interface characteristics:
    - 5, 6, 7, or 8-bit characters
    - Even, odd, or no-parity bit generation and detection
    - l, 1.5 or 2-stop bit generation.
    - Baud generation (DC to 56K baud). 
o   False start bit detection.
o   Complete status reporting capabilities.
o   TRl-STATE TTL drive capabilities for bidirectional data bus and 
    control bus.
o   Line break generation and detection.
o   Internal diagnostic capabilities:
    - Loopback controls for communications link fault isolation.
    - Break, parity, overrun, framing error simulation.
o   Fully prioritized interrupt system controls.


**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
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