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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91
***Info:
The HT21  is an  advanced PC/AT compatible,  single-chip 80386SX/80286
design solution.   This highly  integrated single chip  allows simple,
low cost  system design options while featuring  high performance, low
power  consumption,  and minimum  board  space requirements.  Advanced
memory management features  include support for page mode,  2 or 4-way
interleaving in  both pipelined and  non-pipelined modes. The  LIM 4.0
hardware implementation  features dual sets of 32  registers with full
context support for highest performance Optimization of extended local
memory  accesses. An  advanced  EMS hardware  write-protect option  is
provided. The HT21 supports 256K and 1M DRAMs in l by 1, 1 by 4, and 1
by 9 device configurations for up  to 8MB of on-board system memory. A
flexible Shadow  RAM option for  System and Video  BIOS as well  as 8-
16-bit BIOS Options adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT21 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC  core logic requirements. The chip  also contains all
the  necessary  address buffers,  data  transceivers, memory  drivers,
parity  checking   and  supporting  circuitry  for   a  complete  high
performance computer solution. An asynchronous AT Bus clock allows for
a constant 8MHz Bus clock rate for highest bus device compatibility as
defined in  IEEE Spec P996.   In controlled bus applications  the HT21
supports up to a  12 MHz Bus Clock rate. This device  is packaged in a
208-pin Plastic Quad Flat Pack combining several external buffers into
this space saving solution.

***Configurations:...
***Features:...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
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**W83759/A/F/AF   Advanced VL-IDE Disk Controller                  <96
***Notes:...
***Info:...
***Versions:...
***Features:
o  Pin-to-pin backward compatible with W83759 VL-IDE Interface chip
o  VESA VL-Bus Rev 2.0 compatible, connects directly to local bus and 
   four IDE drives
o  Direct interface to various ANSI ATA/ATA-2/FAST ATA/IDE-2/Enhanced 
   IDE drives
o  Supports 32 and 16-bit data transfer
o  Fully software programmable for command active/recovery time and 
   address setup, data hold time
o  Built-in VL-Bus to 16-bit IO data buffer for special applications
o  Fully supports Enhanced IDE features, including Fast PIO, Mode 3/4, 
   IORDY flow control, prefetch control
o  Supports dual channels to allow up to four drives or non-disk 
   devices (ATAPI CD-ROM and tape drives)
o  Pipeline pre-fetched reads and posted writes for concurrent disk 
   and host operations
o  Independent access timing for all drives (primary/secondary and 
   master/slave)
o  All Enhanced IDE new features may be disabled/enabled via driver 
   or power-on setting by per drive selectability
o  ATA/Mode 0-4 PIO speed may be set as default timing of each drive 
   via power-on jumper setting
o  Supports slave DMA mode protocol (reserved)
o  Supports auto power-down, standby, suspend APM power management 
   state for green PCs
o  Primary and secondary channel can be independently enabled/disabled 
   by software or jumper setting
o  Supports drivers for DOS, Windows, OS/2, UNIX, and Netware
o  Packaged in 100-pin QFP

**W83769          Local Bus IDE Solution                           <94...
**
**UARTS:
**W86C250A  UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
*General Sources:...