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**CS8230 386/AT (82C301/302/303/304/305/306)cFeb87
***Notes:...
***Info:
The CS8230-16-20-25 AT/386 CHIPSet is a seven chip VLSI implementation
of most of the system logic to control an iAPX 386 based system. The
CHIPSet is designed to offer a 100% PC AT compatible integrated
solution. The flexible architecture of the CHIPSet allows it to be
used in any iAPX386 based system design, such as CAD/CAE workstations,
office systems, industrial and financial transaction systems.
CS8230 CHIPSet combined with CHIPs 82C206, Integrated Peripherals
Controller, provides a complete PC AT compatible system using only 40
components plus memory devices.
The CS8230 CHIPSet consists of one 82C301 Bus Controller, one 82C302
Page/Interleave Memory Controller, one each of 82A303 and two 82A304
Address Bus Interfaces, two 82A305 or 82B305 Data Bus Interfaces, and
a 82A306 Control Signal Buffer. An all CMOS CS8232-16, and CS8232-20
CHIPSet allow OEM's to reduce the form factor, size and weight of
their portable, laptop machines due to the reduced power requirements,
the reduced cooling requirements and the reduced buffering
requirements of the CHIPSet. In particular, the all CMOS CS8232-16 and
CS8232-20 CHIPSet will reduce a system's power consumption requirement
by at least half that of an NMOS/BIPOLAR/CMOS based system.
The only difference between the CS8232 CHIPSet and the CS8230 CHIPSet
is that the bipolar parts (82A303, 82A304, 82A305, 82A306) in the
CS8230 CHIPSet have been replaced with CMOS parts (82C303, 82C304,
82C305, 83C306). The difference between the new CMOS parts is that the
drive capability is 12 mA as opposed to 24 mA in the bipolar parts.
The CHIPSet supports a local CPU bus, a 32-bit system memory bus, and
AT buses as shown in the System Block Diagram [see datasheet]. The
82C301 and 82A306/82C306 provide the generation and synchronization of
control signals for all buses. The 82C301 also supports an independent
AT bus clock, and allows for dynamic selection of the processor clock
between the 16-20-25MHz clock and the AT bus clock. The 82A306
provides buffers for bus control signal in addition to other
miscellaneous logic functions.
The 82C302 Page/Interleave Memory Controller provides an interleaved
memory subsystem design with page mode operation. It supports 1 MB to
16 MB of DRAMs with combinations of 256Kbit and 1 Mbit DRAMs. The
processor can operate at 16-20-25 MHz with zero wait state memory
accesses.
The 82A303/82C303 and 82A304/82C304 interface between all address
buses and the addresses needed for proper data path conversion. Two
82A305/82C305/82B305 are used to interface between the local, system
memory, and AT data buses. In addition to having high current drive,
they also perform the conversion necessary between the different sized
data paths.
System Overview
The CS8230 is designed for use in 80386-based systems and provides
complete support for the IBM PC AT bus. There are four buses supported
by the CS8230 as shown in the AT/386 system block diagram [see
datasheet]: the CPU local bus (A and D), the system memory bus (MA and
MD. the IO Channel bus (SA and SD), and the X bus (XA and XD). The
system memory bus is used to interface to DRAM's controlled by the
82C302. The IO channel bus refers to the bus supporting the AT bus
adapters which could be either 8 bit devices or 16 bit devices. The X
bus refers to the peripheral bus to which the DMA controllers and
timers are attached in an IBM PC AT. The X bus has only an 8-bit data
path. The term "AT bus" is used to refer to the IO channel bus and X
bus. Provisions are also made for user extension of the IO channel to
a 32 bit bus.
***Configurations:...
***Features:...
**CS8231 TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306) c86...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:
The 82485 is a second-level cache controller designed to improve the
performance of Intel486 Microprocessor systems. One 82485 cache
controller supports 64K or 128K bytes of second level cache memory
that maps to the entire 4 Gigabytes of the Intel486 microprocessor
address space. The controller is completely software transparent. One
controller plus SRAMs provides a 64K or a 128K cache. External EPROM
can be cached yet remain write protected. The 82485 is fully
compatible with the Intel486 microprocessor. All Intel486 CPU bus
cycles and timings are supported.
A complete, optional second level cache controller using the 82485 is
available as the 485Turbocache Module from Intel (data sheet order
number 240722).
2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically to interface with the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or a non-sectored configuration (one line per tag). The 82485
will directly support a nonsectored 64K data cache or a 128K sectored
data cache. Both the 64K and 128K configurations are able to map the
entire 4 gigabytes of the Intel486 microprocessor address space. The
82485 interfaces directly to the Intel486 microprocessor. All Intel-
486 CPU bus cycles and timings are supported. The 82485 also supports
0 wait state processor operation when there is a cache hit and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations. The controller is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the system bus), so it supports the same cache consistency
mechanisms as the Intel486 CPU. The controller also provides a safe
method to cache ROM BIOS through the use of a write protect pin and a
write protect strapping option.
The data cache (Static RAM) resides external to the 82485. The 82485
provides all controls for the SRAMs. No external latches or tran-
ceivers are required. The 82485 output buffers support up to eight
SRAMs. A 64K cache can be designed with only five components; nine
components for a 128K cache. Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.
The 82485 can be used to design a custom second level cache
configuration. For an easier system design and higher integration, the
82485M Turbocache can be used (see data sheet order number 240722).
This module is a complete second level cache in one package. It
consists of a single 82485 cache controller and SRAM to provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
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*UMC...
**UM82C210 386SX/286 AT Chip Set <91
***Info:...
***Configurations:...
***Features:...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
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