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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*SIS...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:...
***Configurations:...
***Features:
o   Supports Intel/AMD/Cyrix/IDT Pentium CPU Host Bus at 
    66/75/83/95/100 MHz and 2.5/3.3V Bus Interface
    − Supports the Pipelined Address of Pentium compatible CPU
    − Supports the Linear Address Mode of Cyrix CPU
    − 100/100, 95/95, 83/83, 75/75 and 66/66 MHz Synchronous 
      Host/DRAM clocking configuration
    − 100/75, 95/75, 83/66, 66/100 and 66/83 MHz Asynchronous 
      Host/DRAM clocking configuration
    − Supports Host Bus operation for integrated 3D VGA Controller
o   Meets PC99 Requirements
o   Supports PCI Revision 2.2 Specification
o   Integrated Super AGP VGA for Hardware 2D/3D Video/Graphics 
    Accelerators
    − Supports tightly coupled 64 bits 100MHz host interface to VGA 
      to speed up GUI performance and the video playback frame rate
    − Built-in programmable 24-bit true-color RAMDAC up to 230 MHz 
      pixel clock
    − Built-in reference voltage generator and monitor sense circuit
    − Supports loadable RAMDAC for gamma correction in high color 
      and true color modes
    − Built-in dual-clock generator
    − Supports Multiple Adapters and Multiple Monitors
    − Built-in PCI multimedia interface
    − Flexible design for shared frame buffer or local frame buffer 
      architecture
    − Shared System Memory Area 2MB, 4MB and 8MB
    − Supports SDRAM and SGRAM local frame buffer and memory size up 
      to 8 MB
    − Supports Digital Flat Panel Port for Digital Monitor (LCD Panel)
    − Supports DVD H/W Accelerator
o   Integrated Second Level ( L2 ) Cache Controller
    − Write Back Cache Mode
    − Direct Mapped Cache Organization
    − Supports Pipelined Burst SRAM
    − Supports 256K/512K/1M/2M Bytes Cache Sizes
    − Cache Hit Read/Write Cycle of 3-1-1-1
    − Cache Back-to-Back Read Cycle of 3-1-1-1-1-1-1-1
    − Supports Single Read Allocation for L2 Cache
    − Supports Concurrency of CPU to L2 cache and Integrated A.G.P. 
      VGA master to DRAM accesses
o   Integrated DRAM Controller
    − Supports up to 3 double sided DIMMs (6 rows memory)
    − Supports 8Mbytes to 1.5 GBytes of main memory
    − Supports Cacheable DRAM Sizes up to 256 MBytes
    − Supports 1M/2M/4M/8M/16M/32M x N for 2-bank or 4-bank SDRAM
    − Supports 3.3V DRAM
    − Supports Concurrent Write Back
    − Supports CAS before RAS Refresh, Self Refresh
    − Supports Relocation of System Management Memory
    − Programmable CS#, DQM#, SRAS#, SCAS#, RAMWE# and MA Driving 
      Current
    − Option to Disable Local Memory in Non-cacheable Regions
    − Entries GART cache to Minimize the Number of Memory Bus Cycles 
      Required for Accessing Graphical Texture Memory
    − Programmable Counters to Ensure Guaranteed Minimum Access Time 
      for Integrated A.G.P. VGA, CPU, and PCI accesses
    − Two Programmable Non-cacheable Regions
    − Supports X-1-1-1/X-2-2-2 Burst Write Cycles
    − Fully Configurable for the Characteristic of Shadow RAM (640 
      KBytes to 1 MBytes)
    − Shadow RAM in Increments of 16 KBytes Built-in 8 Way 
      Associative/16
    − Supports SDRAM 7/8-1-1-1 Burst Read Cycles
o   Provides High Performance PCI Arbiter
    − Supports up to 4 PCI Masters
    − Supports Rotating Priority Mechanism
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead
    - Supports Concurrency between CPU to Memory and PCI to PCI
    - Supports Concurrency between CPU to 33Mhz PCI Access and 33Mhz 
      PCI to integrated A.G.P. VGA Access
    - Programmable Timers Ensure Guaranteed Minimum Access Time for 
      PCI Bus Masters, and CPU
o   PCI Bus Interface
    - Supports 32-bit PCI local bus standard Revision 2.2 compliant
    - Integrated write-once subsystem vendor ID configuration register
    - Supports zero wait-state memory mapped I/O burst write
    - Integrated 2 stages PCI post-write buffer to enhance frame 
      buffer write performance
    - Integrated 256 bits read cache to enhance frame buffer read 
      performance
    - Supports full 16-bit re-locatable VGA I/O address decoding
o   Integrated Host-to-PCI Bridge
    - Supports Asynchronous PCI Clock
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Zero Wait State Burst Cycles
    - Supports Pipelined Process in CPU-to-PCI Access
    - Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
    - Supports Memory Remapping Function for PCI master accessing 
      Graphical Window
o   Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
    - Supports Graphic Window Size from 4MBytes to 256MBytes
    - Supports Pipelined Process in CPU-to-Integrated 3D A.G.P. 
      VGA Access
    - Supports 8 Way, 16 Entries Page Table Cache for GART to enhance 
      Integrated A.G.P. VGA Controller Read/Write Performance
    - Supports PCI-to-PCI bridge function for memory write from 33Mhz 
      PCI bus to Integrated A.G.P. VGA
o   Integrated Posted Write Buffers and Read Prefetch Buffers to 
    Increase System Performance
    - CPU-to-Memory Posted Write Buffer (CTMFF) with 12QW Deep, Always 
      Sustains 0 Wait Performance on CPU-to-Memory
    - CPU-to-Memory Read Buffer with 4 QW Deep
    - CPU-to-PCI Posted Write Buffer with 2 QW Deep
    - PCI-to-Memory Posted Write Buffer with 8 QW Deep, Always 
      Streams 0 Wait Performance on PCI-to/from-Memory Access
    - PCI-to-Memory Read Prefetch Buffer with 8 QW Deep
    - CPU-to-VGA Posted Write Buffer with 4 QW Deep
o   Fast PCI IDE Master/Slave Controller
    - Bus Master Programming Interface for Windows 98 Compliant 
      Controller
    - Plug and Play Compatible
    - Supports Scatter and Gather
    - Supports Dual Mode Operation - Native Mode and Compatibility 
      Mode
    - Supports IDE PIO Timing Mode 0, 1, 2 ,3 and 4
    - Supports Multiword DMA Mode 0, 1, 2
    - Supports Ultra DMA 33/66
    - Two Separate IDE Bus
    - Two 16 DW FIFO for PCI Burst Transfers.
o   Supports NAND Tree for Ball Connectivity Testing
o   576-Balls BGA Package
o   3.3V Core with mixed 2.5V, 3.3V and 5V I/O CMOS Technology

**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O)                          c97
***Info:
GENERAL DESCRIPTION

This data sheet covers  two products: W83977F/G, and W83977AF/AG whose
pin assignment, and most of the functions are the same. W83977AF/AG is
an advanced version of W83977F/G featuring the FIR function.

W83977F/G,  W83977AF/AG  are  evolving  products from  Winbond’s  most
popular I/O chip  W83877F -- which integrates the  disk drive adapter,
serial  port  (UART),  IrDA   1.0  SIR,  parallel  port,  configurable
plug-and-play  registers  in one  chip  ---  plus additional  powerful
features: ACPI, 8042 keyboard controller with PS/2 mouse support, Real
Time  Clock,  14  general  purpose  I/O  ports,  full  16-bit  address
decoding, TV  remote IR (Consumer  IR, supporting NEC,  RC-5, extended
RC-5, and  RECS-80 protocols).  In addition,  W83977AF/AG provides the
functions of IrDA 1.1 (MIR for 1.152M bps or FIR for 4M bps).

The disk  drive adapter functions of W83977F/G,  W83977AF/AG include a
floppy  disk drive  controller compatible  with the  industry standard
82077/  765, data  separator, write  pre-compensation  circuit, decode
logic, data  rate selection, clock generator,  drive interface control
logic,  and  interrupt/  DMA   logic.  The  wide  range  of  functions
integrated onto the W83977F/G,  W83977AF/AG greatly reduces the number
of components  required for interfacing  with floppy disk  drives. The
W83977F/G, W83977AF/AG supports up to four 360K, 720K, 1.2M, 1.44M, or
2.88M disk drives  and data transfer rates of 250  Kb/s, 300 Kb/s, 500
Kb/s,1 Mb/s, and 2 Mb/s.

The W83977F/G, W83977AF/AG provide two high-speed serial communication
ports (UARTs),  one of  which supports serial  Infrared communication.
Each UART  includes a 16-byte  send/receive FIFO, a  programmable baud
rate  generator, complete  modem control  capability, and  a processor
interrupt  system. Both  UARTs  provide legacy  speed  with baud  rate
115.2k and provide advanced speed  with baud rate 230k, 460k, and 921k
bps  which support  higher speed  modems.  W83977AF/AG  alone provides
independent 3rd UART (32-byte FIFO) dedicated for IR function.

The  W83977F/G, W83977AF/AG  supports one  PC-compatible  printer port
(SPP), Bi-directional  Printer port  (BPP) and also  Enhanced Parallel
Port (EPP)  and Extended Capabilities Port (ECP).  Through the printer
port  interface  pins, also  available  are:  Extension  FDD Mode  and
Extension 2FDD Mode allowing one or two external floppy disk drives to
be connected.

The   configuration  registers   support   mode  selection,   function
enable/disable,  and power down  function selection.  Furthermore, the
configurable  PnP  features  are  compatible  with  the  plug-and-play
feature demand of Windows 95TM, which makes system resource allocation
more efficient than ever.

W83977F/G,  W83977AF/AG  provides  functions  that  comply  with  ACPI
(Advanced Configuration  and Power Interface),  which includes support
of  legacy and  ACPI  power  management through  SMI  or SCI  function
pins. W83977F/G, W83977AF/AG also  has auto power management to reduce
power consumption.

The keyboard  controller is based  on 8042 compatible  instruction set
with a 2K Byte programmable ROM and a 256-Byte RAM bank. Keyboard BIOS
firmware is available with  optional AMIKEY-2, Phoenix MultiKey/42, or
customer code.

The  W83977F/G, W83977AF/AG  provides a  set of  flexible  I/O control
functions to the system designer  through a set of General Purpose I/O
ports. These GPIO ports may serve as simple I/O or may be individually
configured to provide a pre-defined alternate function.

W83977F/G,  W83977AF/AG is made  to fully  comply with  Microsoft PC97
Hardware Design Guide. IRQs, DMAs, and I/O space resource are flexible
to adjust to meet ISA PnP requirement. Full 16-bit address decoding is
also  provided. Moreover W83977F/G,  W83977AF/AG is  made to  meet the
specification of PC97‘s requirement  in the power management: ACPI and
DPM (Device Power Management).

***Versions:...
***Features:...
**W83977TF        WINBOND I/O (Multi I/O)                          c97...
**W83977EF        WINBOND I/O (Multi I/O)                          <98...
**W83977ATF       WINBOND I/O (Multi I/O)                          <98...
**
**Disk Controller:
**W83759/A/F/AF   Advanced VL-IDE Disk Controller                  <96...
**W83769          Local Bus IDE Solution                           <94...
**
**UARTS:
**W86C250A  UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
*General Sources:...

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