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**82396SX Smart Cache 12/17/90
***Notes:...
***Info:
The 82396SX Smart Cache (part number 82396SX) is a low cost, single
chip, 16-bit peripheral for Intel's i386 SX Microprocessor. By
storing frequently accessed code or data from main memory the 82396SX
Smart Cache enables the i386 SX Microprocessor to run at near zero
wait states. The dual bus architecture allows another bus master to
access the System Bus while the i386 SX Microprocessor operates out of
the 82396SX Smart Cache on the Local Bus. The 82396SX Smart Cache has
a snooping mechanism which maintains cache coherency with main memory
during these cycles.
The 823968X Smart Cache is completely software transparent, protecting
the integrity of system software. The advanced architectural features
of the 82596SX Smart Cache offer high performance with a cache data
RAM size that can be integrated on a single chip, offering the board
space and cost savings needed in an i386 SX Microprocessor based
system.
1.0 823968X SMART CACHE FUNCTIONAL OVERVIEW
1.1 Introduction
The primary function of a cache is to provide local storage for freq-
uently accessed memory locations. The cache intercepts memory
references and handles them directly without transferring the request
to the System Bus. This results in lower traffic on the System Bus and
decreases latency on the Local Bus. This leads to improved performance
for a processor on the Local Bus. It also increases potential system
performance by reducing each processor's demand for System Bus band-
width, thus allowing more processors or system masters in the system.
By providing fast access to frequently used code and data the cache is
able to reduce the average memory access time of the i386 SX
Microprocessor based system.
The 82396SX Smart Cache is a single chip cache subsystem specifically
designed for use with the i386 SX Microprocessor. The 82396SX Smart
Cache integrates 16KB cache, the Cache Directory and the cache control
logic onto one chip. The cache is unified for code and data and is
transparent to application software. The 82396SX Smart Cache provides
a cache consistency mechanism which guarantees that the cache has the
most recently updated version of the main memory. Consistency sup-
port has no performance impact on the i386 SX Microprocessor. Section
1.2 covers all the 82396SX Smart Cache features.
The 82396SX Smart Cache architecture is similar to the i486 SX
Microprocessor's on-chip cache. The cache is four Way SET associative
with Pseudo LRU (Least Recently Used) replacement algorithm. The line
size is 16B and a full line is retrieved from the memory for every
cache miss. A TAG is associated with every 16B line. The 82396SX Smart
Cache architecture allows for cache read hit cycles to run on the
Local Bus even when the System Bus is not available. 82396SX Smart
Cache incorporates a new write buffer cache architecture, which allows
the i386 SX Microprocessor to continue operation without waiting for
write cycles to actually update the main memory.
A detailed description of the cache operation and parameters is
included in Chapter 2.
The 82396SX Smart Cache has an interface to two electrically isolated
busses. The interface to the i386 SX Microprocessor bus is referred to
as the Local Bus (LB) interface. The interface to the main memory and
other system devices is referred to as the 82396SX Smart Cache System
Bus (SB) interface. The SB interface emulates the i386 SX
Microprocessor. The SB interface, as does the i386TM SX Micro-
processor. operates in pipeline mode.
In addition, it is enhanced by an optional burst mode for Line Fills.
The burst mode provides faster line fills by allowing consecutive read
cycles to be executed at a rate of up to one word per clock
cycle. Several bus masters (or several 82396SX Smart Caches) can share
the same System Bus and the arbitration is done via the SHOLD/SHLDA
mechanism (similar to the i486 SX Microprocessor).
Cache consistency is maintained by the SAHOLD/SEADS# snooping
mechanism, similar to the i486 SX Microprocessor. The 82396SX Smart
Cache is able to run, a zero wait state i386 SX Microprocessor
non-pipelined read cycle if the data exists in the cache. Memory write
cycles can run with zero wait states if the write buffer is not full.
The 82396SX Smart Cache organization provides a higher hit rate than
other standard configurations. The 82396SX Smart Cache, featuring the
new high performance write buffer cache architecture, provides full
concurrency between the electrically isolated Local Bus and System
Bus. This allows the 82396SX Smart Cache to service read hit cycles on
the Local Bus while running line fills or buffered write cycles on the
System Bus.
1.2 Features
1.2.1 823858X-LIKE FEATURES
o The 82396SX Smart Cache maps the entire physical address range of
the i386 SX Microprocessor (16MB) into an 16KB cache. Unified code
and data cache.
o Cache attributes are handled by hardware. Thus the 82396SX Smart
Cache is transparent to application software. This preserves the
integrity of system software and protects the users software
investment.
o Word and Byte writes, Word reads.
o Zero wait states in read hits and in buffered write cycles. All i386
SX Microprocessor cycles are non-pipelined (Note: The i386 SX
Microprocessor must never be pipelined when used with the 82396SX
Smart Cache - NA# must be tied to Vcc).
o A hardware cache FLUSH# option. The 82396SX Smart Cache will
invalidate all the Tag Valid bits in the Cache Directory and clear
the System Bus line buffer when FLUSH# is activated tor a minimum of
four CLK’s.
o The 82396SX Smart Cache supports non-cacheable accesses.
o The 82396SX Smart Cache internally decodes the i387 SX Math
Coprocessor accesses as Local Bus cycles.
o The System Bus interface emulates a i386 SX Microprocessor
interface.
o The 82396SX Smart Cache supports pipelined and non-pipelined system
interface.
o Provides cache consistency (snooping): The 82396SX Smart Cache
monitors the System Bus address via SEADS# and invalidates the cache
address if the System Bus address matches a cached location.
1.2.2 NEW FEATURES
o 16KB on chip cache arranged in four banks, one bank for each way. In
Read hit cycles, one word is read. In a write hit cycle, any byte
within the word can be written. In a cache fill cycle, the whole
line (16B) is written. This large line size increases the hit rate
over smaller line size caches.
o Cache architecture similar to the i486 SX Microprocessor cache: 4
Way set associative with Pseudo LRU replacement algorithm. Line
size is 16B and a full line is retrieved from memory for every cache
miss. A Tag Valid Bit and a Write Protect Bit are associated with
every Line.
o New write buffer architecture with four word deep write buffer
provides zero wait state memory write cycles. I/O, Halt/ Shutdown
and LOCK#ed writes are not buffered.
o Concurrent Line Buffer Cacheing: The 82396SX Smart Cache has a line
buffer that is used as additional memory. Before data gets written
to the cache memory at the completion of a Line Fill it is stored in
this buffer. Cache hit cycles to the line buffer can occur before
the line is written to the cache.
o In i387 SX Math Coprocessor accesses, the 82396SX Smart Cache drives
the READYO# in one wait state if the READYI# was not driven in the
previous clock.
Note that the timing of the 82396SX Smart Cache’s READYO# generation
for i387 SX Math Coprocessor cycles is incompatible with 80287
timing.
o An enhanced System Bus interface:
a) Burst Option is supported in line-fills similar to the i486 SX
Microprocessor. SBRDY# (System Burst READY) is provided in
addition to SRDY#. A burst is always a 16 byte line fill (cache
update) which is equivalent to eight word cycles.
b) System cacheability attribute is provided (SKEN#). SKEN# is used
to determine whether the current cycle is cacheable. It is used
to qualify Line Fill requests.
c) SHOLD/SHLDA system bus arbitration mechanism is supported. A
Multi i386 SX 82396SX Smart Cache cluster can share the same
System Bus via this mechanism.
f) Cache invalidation cycles supported via SEAD$#. This is used to
provide cache coherency.
o Full Local Bus/System Bus concurrency is attained by:
a) Servicing cache read hit cycles on the Local Bus while completing
a Line Fill on the System Bus. The data requested by the i386 SX
Microprocessor is provided over the local bus as the first word
of the Line Fill.
b) Servicing cache read hit cycles on the Local Bus while executing
buffered write cycles on the system bus.
c) Servicing cache read hit cycles on the Local Bus while another
bus master is running (DMA, other i386 SX Microprocessor, 82396SX
Smart Cache, i486 SX Microprocessor, etc...) on the System Bus.
d) Buffering write cycles on the Local Bus while the system bus is
executing other cycles. Write protected areas are supported by
the SWP# input. This enables caching of ROM space or shadowed ROM
space.
o No Post Input (NPI#) provided for disabling of write buffers per
cycle. This option supports memory mapped l/O designs.
o Byte Enable Mask (BEM) is provided to mask the processor byte
enables during a memory read cycle.
o A2oM# input provided for emulation of 8086 address wrap-around.
o SRAM test mode, in which the TAGRAM and the cache RAM are treated as
standard SRAM, is provided. A Tristate Output test mode is also pro-
vided for system debugging. In this mode the 82396SX Smart Cache is
isolated from the other devices in the board by floating all its
outputs.
o Single chip, 132 lead PQFP package, 1 micron CHMOS-IV technology.
***Versions:...
***Features:...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*Winbond...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O) c97
***Info:
GENERAL DESCRIPTION
This data sheet covers two products: W83977F/G, and W83977AF/AG whose
pin assignment, and most of the functions are the same. W83977AF/AG is
an advanced version of W83977F/G featuring the FIR function.
W83977F/G, W83977AF/AG are evolving products from Winbond’s most
popular I/O chip W83877F -- which integrates the disk drive adapter,
serial port (UART), IrDA 1.0 SIR, parallel port, configurable
plug-and-play registers in one chip --- plus additional powerful
features: ACPI, 8042 keyboard controller with PS/2 mouse support, Real
Time Clock, 14 general purpose I/O ports, full 16-bit address
decoding, TV remote IR (Consumer IR, supporting NEC, RC-5, extended
RC-5, and RECS-80 protocols). In addition, W83977AF/AG provides the
functions of IrDA 1.1 (MIR for 1.152M bps or FIR for 4M bps).
The disk drive adapter functions of W83977F/G, W83977AF/AG include a
floppy disk drive controller compatible with the industry standard
82077/ 765, data separator, write pre-compensation circuit, decode
logic, data rate selection, clock generator, drive interface control
logic, and interrupt/ DMA logic. The wide range of functions
integrated onto the W83977F/G, W83977AF/AG greatly reduces the number
of components required for interfacing with floppy disk drives. The
W83977F/G, W83977AF/AG supports up to four 360K, 720K, 1.2M, 1.44M, or
2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500
Kb/s,1 Mb/s, and 2 Mb/s.
The W83977F/G, W83977AF/AG provide two high-speed serial communication
ports (UARTs), one of which supports serial Infrared communication.
Each UART includes a 16-byte send/receive FIFO, a programmable baud
rate generator, complete modem control capability, and a processor
interrupt system. Both UARTs provide legacy speed with baud rate
115.2k and provide advanced speed with baud rate 230k, 460k, and 921k
bps which support higher speed modems. W83977AF/AG alone provides
independent 3rd UART (32-byte FIFO) dedicated for IR function.
The W83977F/G, W83977AF/AG supports one PC-compatible printer port
(SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel
Port (EPP) and Extended Capabilities Port (ECP). Through the printer
port interface pins, also available are: Extension FDD Mode and
Extension 2FDD Mode allowing one or two external floppy disk drives to
be connected.
The configuration registers support mode selection, function
enable/disable, and power down function selection. Furthermore, the
configurable PnP features are compatible with the plug-and-play
feature demand of Windows 95TM, which makes system resource allocation
more efficient than ever.
W83977F/G, W83977AF/AG provides functions that comply with ACPI
(Advanced Configuration and Power Interface), which includes support
of legacy and ACPI power management through SMI or SCI function
pins. W83977F/G, W83977AF/AG also has auto power management to reduce
power consumption.
The keyboard controller is based on 8042 compatible instruction set
with a 2K Byte programmable ROM and a 256-Byte RAM bank. Keyboard BIOS
firmware is available with optional AMIKEY-2, Phoenix MultiKey/42, or
customer code.
The W83977F/G, W83977AF/AG provides a set of flexible I/O control
functions to the system designer through a set of General Purpose I/O
ports. These GPIO ports may serve as simple I/O or may be individually
configured to provide a pre-defined alternate function.
W83977F/G, W83977AF/AG is made to fully comply with Microsoft PC97
Hardware Design Guide. IRQs, DMAs, and I/O space resource are flexible
to adjust to meet ISA PnP requirement. Full 16-bit address decoding is
also provided. Moreover W83977F/G, W83977AF/AG is made to meet the
specification of PC97‘s requirement in the power management: ACPI and
DPM (Device Power Management).
***Versions:...
***Features:...
**W83977TF WINBOND I/O (Multi I/O) c97...
**W83977EF WINBOND I/O (Multi I/O) <98...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96...
**W83769 Local Bus IDE Solution <94...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
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