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**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
**HTK320 386DX Chip Set c:Sep91
***Info:
The HTK320 chip set is a 2-chip, high-performance, cost-effective
solution for the 80386DX microprocessor. In its minimum configuration,
this highly integrated chip set requires only four external TTL
devices to implement a fully compatible IBM PC/AT system at speeds up
to 40 MHz.
The HTK320 is based on Headland’s Bus Architecture and consists of the
HT321-ISA Controller and the HT322-Memory Control Unit (MCU) packaged
in two 184-pin plastic quad flat packs. Among its features are an
on-chip cache controller and internal tag RAM.
Unlike other 3rd generation chip sets that have integral Cache
Controllers, the HTK320 integrates the high-speed tag RAM into the
chip set to enhance performance and significantly reduce component
count and manufacturing cost. The direct mapped or 2-way set
associative cache design supports external cache sizes of 32K, 64K,
and 128K.
The HTK320 can support Peripheral Devices such as VGA or SCSI
controllers on the local processor bus, or any 3rd party device that
is designed to work within the 386DX Bus Protocol and Timing. By
eliminating the ISA backplane bottleneck, system designers can greatly
improve the performance of functions such as graphics generation and
disk access.
The HTK320 incorporates a 4-leve1 deep Write Buffer and performs byte
gathering into 32 bit accesses to the DRAM. This facilitates real
zero wait state writes and, when coupled with the 2-way set
associative cache, provides enhanced memory performance.
The HTK320 Supports up to 4 banks of DRAM, configurable as 1-4 Banks.
This flexible memory architecture allows for any memory type, from
256Kb to 16Mb devices, in any bank. Maximum system performance is
achieved from the DRAM banks through various means, including
interleave of Memory Bank and/or Page, and CAS before RAS refresh.
The memory may also be tuned to its maximum potential through the use
of extensive DRAM timing Control Registers, controls include,
Precharge time, Access time on Reads, Active time on Writes, as well
as CAS and RAS delays. In addition, further system performance is
gained by separate timing parameters on the read and Write cycles
which allow system designers to take maximum advantage of the
pipelined structure of the chip set.
The HTK320 also supports extensive mapping registers, which allow
system designers to take maximum advantage of system memory. The chip
set supports EMS LIM 4.0, allows for mixed Shadow/Remap in 16K blocks
between the 640K and 1M boundaries, and eliminates the requirement fer
external decoding logic by support of 27 Programmable Non-cache
regions. With the' extensive HTK320 mapping capability, it is
feasible to seamlessly place 3rd party devices on the local bus
without the need for external TTL support. The HTK320 Mapping
structure provides for a single 8-bit EPROM to be used for both the
system and Video BIOS, further reducing the system chip count and
cost.
***Configurations:...
***Features:...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W83877F WINBOND I/O (Multi I/O) <96
***Info:...
***Versions:...
***Features:
FDC:
o Compatible with IBM PC AT disk drive systems
o Variable write pre-compensation with track selectable capability
o DMA enable logic
o Non-burst mode DMA option
o Supports floppy disk drives and tape drives
o Detects all overrun and underrun conditions
o Data rate and drive control registers
o Built-in address mark detection circuit to simplify the read
electronics
o IBM PC system address decoder
o Supports up to two embedded hard disk drives (IDE AT BUS)
o Single 24 MHz crystal input
o FDD anti-virus functions with software write protect and FDD write
enable signal, write data signal force inactive
o Supports up to four 3.5-inch or 5.25-inch floppy disk drives
o Completely compatible with industry standard 82077
o 360K/720K/1.2M/1.44M/2.88M format
o 250K, 300K, 500K, 1M bps data transfer rate
o Supports vertical recording format
o 16-byte data FIFOs
UART:
o Two high-speed 16550 compatible UARTs with 16-byte send/receive
FIFOs
o MIDI compatible
o Fully programmable serial-interface characteristics:
- 5, 6, 7 or 8-bit characters
- Even, odd or no parity bit generation/detection
- 1, 1.5 or 2 stop bits generation
o Internal diagnostic capabilities:
- Loop-back controls for communications link fault isolation
- Break, parity, overrun, framing error simulation
o Programmable baud generator allows division of 1.8461 MHz and 24
MHz by 1 to (2^16-1)
Parallel Port:
o Compatible with IBM parallel port
o Supports parallel port with bidirectional lines
o Supports Enhanced Parallel Port (EPP)
- Compatible with IEEE 1284 specification
o Supports Extended Capabilities Port (ECP)
- Compatible with IEEE 1284 specification
o Extension FDD mode supports disk drive B through parallel port
o Extension Adapter Mode supports pocket devices through parallel port
o Extension 2FDD mode supports disk drives A and B through parallel
port
o JOYSTICK mode supports joystick through parallel port
Others:
o Programmable configuration settings
o Immediate or automatic power-down mode for power management
o All hardware power-on settings have internal pull-up or pull-down
resistors as default value
o Packaged in 100-pin QFP
o Configurable Plug and Play registers
o Infrared communication port
**W83877TF/TG/TD WINBOND I/O (Multi I/O) c97...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O) c97...
**W83977TF WINBOND I/O (Multi I/O) c97...
**W83977EF WINBOND I/O (Multi I/O) <98...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96...
**W83769 Local Bus IDE Solution <94...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
*ZyMOS...
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