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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C701 FireStar Plus c:97
***Notes:...
***Info:
Overview
This section describes the follow-on chip to the OPTi FireStar ACPI
solution, the FireStar Plus. The key features of this new product can
be summarized as follows.
o Mostly backward-compatible in pin function and register set with
FireStar ACPI (some PIO functions have been moved from critical
pins to improve timing)
o Implements ATA-33 (Ultra DMA) IDE Interface, with support for all
modes
o Supports 2.5V CPUs
o Incorporates MA13 support for 64Mb SDRAM chips
o Incorporates 64Mb EDO DRAM support
o Enables use of synchronous DRAM on all six banks (original
FireStar chip limited synchronous DRAM to the first four banks)
o Allows redefinition of many interface pins for better utilization
of chipset PIO features (many new function pins are easily
available)
Features
The following paragraphs describe the feature set changes between
FireStar ACPI and FireStar Plus.
Ultra DMA IDE Interface
The ATA33 specification for synchronous bus mastering IDE, also known
as Ultra DMA, is fully supported by FireStar Plus.
Synchronous DRAM on All Banks
The original FireStar chip supports synchronous DRAM only on RAS0-3#.
FireStar Plus also supports synchronous DRAM on RAS4-5#. The
additional functionality is selected through register bits that are
already defined on the FireStar ACPI part.
2.5V CPU Interface
FireStar Plus supports newer CPUs with I/O voltage requirements as low
as 2.5V. The pin redefinition is as follows.
o Pins E8, G5, T5, and W5 are now VCC_CPU and can be powered at 2.5V
or 3.3V.
o Pins K5, H22, and AB19 are now VCC_CORE and must always be powered
at 3.3V.
o Pin M5, CPUCLKIN, must receive a clock on the VCC_CPU plane. So if
a 2.5V CPU is used, this clock should also be 2.5V.
The 2.5V interface is a strap-selected option. It is selected by a
strap on pin B7 (new MA13 pin). If B7 is sensed low at reset, the CPU
interface is 3.3V; if sensed high along with TMS (pin AB5) low, the
CPU interface is 2.5V.
Redefinition of DRQ/DACK# Interface
The 7 pins assigned to DACK0-7# can be redefined to improve avail-
ability of PIO pins.
While the new definition only involves circuit modifications to the
DACK0-7# pins, the overall gain is much greater when used with the
82C602A Companion Chip in its Viper Note-book Mode A configuration.
o 8 power management inputs are now available, muxed in with the
DRQs and IRQ8# on the four EPMMUX pins.
o 7 full-featured PIO pins are available on the former FireStar
DRQ0-7 pins and IRQ8# pin. The number of pins is actually 8, but
is reduced b y 1 because one must be programmed as ATCLK/2.
o 12 PPWR outputs are generated by latching the SD bus lines from
PCTLH (FireStar PPWRL) and PCTLL (FireStar RSTDRV).
o The ISA bus RSTDRV signal is now generated by the 82C602A chip, so
that the FireStar RSTDRV pin can be used for PPWR generation
(power control latch control signal). If the extra PPWR signals
are not needed, the FireStar RSTDRV pin becomes useful as a full-
featured PIO pin.
Warnings
1. Until the Extended Mode option has been programmed, DACK3-7# will
be driving out against the signal input muxes. It is therefore
important to ensure that the logic will not be harmed by this
arrangement (the FireStar outputs safely accept being driven by
external logic in this mode).
2. EDACKEN is an option used to ensure proper ISA master operation.
It prevents the EDACK decoder from glitching its DACK# outputs during
EDACK switching. If ISA masters are not supported in the system, this
option is not needed (tie the EDACK line high on the 82C602A).
3. There are no provisions to block conflicts in case more than one
pin is programmed to the same function. For example, if a PIO pin is
programmed to be ACPI8-11, and the Extended Mode option also enables
EPMMUX1 to bring in ACPI8-11, the results are unpredictable.
***Configurations:...
***Features:...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD7625 Desktop Buffer Manager <10/01/92
***Info:...
***Versions:...
***Features:...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:
SYSTEMS LOGIC/PERIPHERAL DEVICES
WD16C451, WD16C551 - Enhanced Asynchronous Communications Element (ACE) with Parallel Port
WD16C452, WD16C552 - Dual Enhanced Asynchronous Communications Element (ACE)
WD16C550 Enhanced Asynchronous Communications Element (ACE) with FIFOs
WD76C10AlLP/LV ISA-Based System Controller for 80386SX and 80286 Desktop and Portable Compatibles
WD76C20/LV Floppy Disk Controller, Real Time Clock, IDE Interface, and Support Logic Device
WD76C30/LV Peripheral Controller, Interrupt Multiplexer, and Clock Generator Device
WD7710/LP ISA-Based System Controller with Cache for 80386SX and 80286 Desktop and Portable Compatibles
WD7910/LP ISA-Based System Controller with Cache for 80386SX and 80286 Desktop and Portable Compatibles
IMAGING DEVICES
ICS90C61A Dual Video/Memory Clock Generator
ICS90C63 Dual Video/Memory Clock Generator
ICS90C64 Dual Video/Memory Clock Generator
WD90C00 VGA Controller (8514/A clone, max 1MB, 1024x768x16, 800x600x256)
WD90C01 8514/A for laptops
WD90C10 VGA, 256KB
WD90C11, WD90C11A Enhanced VGA Controller (max 512KB, 1024x768x16, 800x600x256)
WD90C20, WD90C20A VGA Flat Panel Display Controller (800x600x16, 640x460x256, 32 shades gray)
WD90C22 VGA Flat Panel Display Controller (800x600x16, 640x460x256, 64 shades gray)
WD90C24/A/A2 SVGA, max 1MB, 1280x1024x16, 1024x768x16, LCD, VESA-LB, 3.3 or 5V
WD90C26 VGA Flat Panel Display Controller
WD90C30 High Performance Video Controller (max 1MB, 1024x768x256, 1024x768x16)
WD90C31 Accelerator Video Controller (max 1MB, 1024x768x256, 1280x1024x16)
WD90C33 Same as WD90C31 but with, max 2MB, VESA-LB, 1280x1024x256, 1280x1024x16)
WD90C55 VGA LCD Interface
WD90C56 VLBI (Video Local Bus Interface), for WD90C30/31, VESA not mentioned.
WD9710 Pipelined, 32bit core, 64bit RAM, 24bit RAMDAC, PCI/VLB
WD9712 similar to WD9710
STORAGE DEVICES
WD10C01A Winchester Disk Controller
WD10C27 Data Separator
WD33C92A Enhanced SCSI Bus Interface Controller
WD33C93B Enhanced SCSI Bus Interface Controller
WD33C95A, WD33C96A Enhanced Single-ended and Differential SCSI Bus Interface Controller
WD37C65C Floppy Disk Subsystem Controller Device
WD42C22C Winchester Disk Subsystem Controller Device
WD60C318 Optical Disk Drive Encoder/Decoder
WD60C40A Peripheral Cache Manager Device
WD60C80 Error Detection and Correction Chip (EDAC)
WD61C23A High Performance Hard Disk Controller
WD61C40A Peripheral Cache Manager Device
WD7000 ESDI Controller (16-bit ISA)
WD7193 Fast SCSI-II PCI adapter, 33C296A-ZX chip
WD7197 Fast Wide version of WD7193
WD7296A Fast Wide SCSI-II (PCI?), possibly WD34C296 chip
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