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**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf
Information taken from:
1995_Intel_Pentium_Processors_and_Related_Components.pdf*
8249x Cache controllers.pdf**
>* Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95
The info and features section have been solely sourced from the first
source. The second source provides far more detail. Additional
information in the configurations section and below have been sourced
from the second.
"Although the 82497 Cache Controller is part of the Pentium processor
(735\90, 815\100, 1000\120, 1110\133) CPU-Cache Chip Set and the 82496
Cache Controller is part of the Pentium Processor (510\60, 567\66)
Chip Set, the two parts are functionally identical except for the
differences noted in this section." - p491
Aside from some minor differences in pin configuration, the main
difference is the direct support for 3.3V processors. This chipset is
still a 5V part. The cache operates at bus speed, max 66MHz.
This chip was used on the Pentium 90MHz CPU complexes of Intel's
Xpress platform. Specifically the BXCPUPENT90 (Single 90MHz, 16
82492s). Also found on IBM 9595/Server 500 Pentium 90MHz complexes.
***Info:...
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**85C206 Integrated Peripheral Controller [no datasheet] ?
***Notes:...
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**WD7625 Desktop Buffer Manager <10/01/92
***Info:...
***Versions:...
***Features:
ADDRESS BUFFER FEATURES
o Allows WD7SC10A, WD7855, WD8110, WD7710, and WD7910 based designs
with WD7620/30 for laptop or notebook systems
o Will work in three different power supply modes:
- 3.3V only
- 5V only
- Mix mode 3.3V and 5V
o Direct connect to AT Address Bus SA1:19 and LA17:23 with 24 mA
drive
o Power Management Control (PMC) input MUX
o General purpose suspend/resume and power supply control logic
o Fifteen-bit Power Management Control (PMC) output register and
control logic
o Low power request and resume signal delay simplify the design of
the power supply
o Watchdog timer for system idle detection
o DRAM WE signal from WD7xc10 inversion and buffering
o RESIN output generation from reset switch (RSTSW)
o System Reset generation
o Chip select decoding for registers in the WD7625LV Data Buffer
Function
o 144-pin SQFP package
DATA BUFFER FEATURES
o Allows WD7SC10A, WD7855, WD7710, and WD7910 based designs with
WD7620/30 for laptop or notebook systems
o Will work in three different power supply modes:
- 3.3V only
- 5V only
- Mix mode 3.3V and 5V
o Direct connection to AT data bus; 20K integrated pull-up for
SD(0:7)
o Direct connection to IDE data bus
o Two general purpose 8-bit I/O registers:
- Register A
- Register B
o One general purpose 8-bit I/O Register C, with single bit
set/reset control
o One general purpose 1-bit I/O Register Y0
o One 4-bit general purpose input only Register Z
o DRQ multiplexing plus 20K integrated pull-down
o DACK demultiplexing
o SMEMR, SMEMW signals plus 22K internal pull-up
o 144-pin SOFP package
**WD8120LV Super I/O [no datasheet] ?
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