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**M1489/87 FinALi-486 PCI Chipset <Feb95
***Info:...
***Configurations:...
***Features:
Supported CPUs
o Supports AMD 486D4 and X5, Intel 486, P24T, P24D, DX4, SL-
Enhanced, Cyrix M7, UMC U5 and AMD AM486DXL CPUs in 25, 33, 40,
50, 66, 100 and 133 MHz 3V/5V CPU interface
o Supports CPU L1 writeback
o Supports Cyrix's linear addressing
L2 Cache Controller
o Write Back cache with standard SRAM
o 8 Tag Bit, always force Dirty or 7 Tag Bit, 1 Dirty bit
o Supports cache size of 128K to 1M with 32KX8, 64Kx8, 128Kx8
o Supports 2-1-1-1 read burst timing
o Write hit 0 wait support
DRAM Controller
o Supports 5V/3V EDO DRAM
o Flexible DRAM type & Timing support
o Supports up to 128M bytes, 4-bank DRAM size
o Supports hidden refresh and RAS only normal refresh
Built in RTC & KBC
o Built in 128 byte Real Time Clock (RTC) & MC14069
o Built in Keyboard Controller (KBC) & 7406
Built in IDE Controller
o Dedicated IDE pins, concurrent with PCI bus
o 4x32 bits Read-Ahead buffer and Write-Post buffer support
o Supports through ATA PIO mode 3, 4 harddisk
PCI Local Bus
o Synchronous 20, 25, 33 MHz PCI clock
o Supports PCI rev 2.0 with 4 PCI devices, 3 slot PCI masters, 1
slot PCI slave
o Supports 4 PCI interrupt steering input
o Supports CPU to PCI 4 layer DWord write buffer
o Supports PCI to memory 8 layer DWord write buffer
o Supports PCI parity
Power Management
o Deep Green SMM, SMI
o Suspend switch support, Green mode state is LED indicated
o CLKCTR for clock generator control
Process/Packing
o M1489 0.6u, 208-pin PQFP
o M1487 0.6u, 160-pin PQFP
**M???? Genie, Quad Pentium [no datasheet, some info] c95...
**M1451/49 Aladdin (Pentium) [no datasheet] ?...
**M1511/12/13 Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23 Aladdin III 50-66MHz <Nov96...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
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*Unresearched:...
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*Western Digital...
**WD7625 Desktop Buffer Manager <10/01/92
***Info:
INTRODUCTION
This document describes the two separate functions, Address Buffer and
Data Buffer, available in the WD7625LV chip. A strapping input pin
selects the Data Buffer Function when strapped low, otherwise it
selects the Address Buffer Function.
GENERAL DESCRIPTION
The WD7625LV is a combination design which includes two separate
functions: Address Buffer and Data Buffer in one chip. A strapping
input pin selects the Data Buffer Function if it is strapped low;
otherwise, it selects the Address Buffer Function. For designs that
use both the data buffer and the address buffer functions, two
WD7625LV devices are needed in the system.
In the Address Buffer Function, the WD7625LV is an address buffer and
power management chip.
In the Data Buffer Function, the WD7625LV is a data buffer, IDE buffer
and I/O register device for the WD7x00 16-bit chip sets.
***Versions:...
***Features:...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
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