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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92
***Info:
The OPTi 82C497 is a Direct Mapped Write Back cache controller with
one level write buffer that is an optional part of the DXBB (Building
Block) Chip set. The DXBB also contains the 82C496 and the 82C206,
which form the heart of the system. The 82C497 is added to the DXBB
chip set for cache based systems.
The OPTi 82C496 offers an upgradable CPU module base-board solution
for the 80386 or the 80486 PC/AT system. By swapping the CPU module,
the vendor can configure the 82C496 driven base-board into various
32-bit AT systems - 386 or 486 CPU, with cache or without cache and
rated at 16MHz- 50MHz.
For the Non-Cache systems, the CPU interfaces directly with the 82C496
and the local devices, like the local VGA controller or the local hard
disk adaptor.
For cache based systems the 82C497 (the cache controller) sits between
the CPU and the 82C496 and the local devices. All the high frequency
signals are isolated by the 82C497. This allows the base-board to run
at a fixed speed (25 or 33MHz) - while the CPU and the Cache can run
synchronously at any determined rated speed. This provides a reliable
upgrade method for the CPU modules.
***Configurations:...
***Features:...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91
***Info:...
***Versions:...
***Features:
o 84-pin PLCC and PQFP packages
o 5V supply requirement (WD76C20)
3.3V supply requirement (WD76C20LV)
o 3.0V battery backup supply for the RTC and 114 byte SRAM (WD76C20)
2.4V battery backup supply for the RTC and 114 byte SRAM
(WD76C20LV)
o Implemented in a low-power, high-performance, 1.25 micron CMOS
technology process
o Floppy Disk Controller (FDC) software transparent power-down mode
with low standby ICC current. FOC features:
- 256 tracks support
- 100% software compatible with NEC 765A
- Integrated high-performance DPLL data separator:
- 125, 250, 300, 500 Kb/sec and 1 Mb/sec data rates
- Option to select 150 Kb/sec FM and 300 Kb/sec MFM data
rates only
- Automatic Write Precompensation:
- Defeat option
- Inner track value of 125 or 187 ns pin selectable
- On chip clock generation:
- 2 TTL clock inputs, or
- Single 16 or 32 MHz crystal circuit and one TTL clock input
- Power Qualified Reset
- Enable PQR in W076C20
- Disable PQR in W076C20LV
- Host interface read/write accesses compatible with 80286
microprocessors at speeds up to 12 MHz with 0 wait states
- Direct floppy disk drive interface - no buffers needed
- 48 mA sink output drivers
- Schmitt Trigger input line receivers
- FDC direct PC XT/AT interface compatibility
- Floppy Control and Operations Registers on chip
- In PC/AT mode, provides required signal qualification to DMA
channel
- IBM BIOS compatible
- Dual-speed spindle drive support
- PS/2 type drive support
o Real Time Clock (RTC) features:
- Software compatible with Motorola MC146818A.
- Internal time base and oscillator circuitry
- Counts seconds, minutes, and hours
- Counts days of the week, date, month, and year
- Time base input for 32.768 KHz square wave
- Time base oscillator for parallel resonant crystals
- Binary or BCD representation of time, calendar, and alarm
- 12- or 24-hour clock with AM and PM in 12-hour mode
- Daylight savings time option
- Automatic leap year compensation
- Interfaced with software as 128 RAM locations
- 114 bytes at general purpose RAM
- Status bit indicates data integrity
- Bus compatible interrupt signals (IRQ)
- Three interrupts are separately software maskable and testable:
- Time-at-day alarm - once-per-second to once-per-day
- Periodic interrupt rates tram 122 us to 500 ms
- End-at-clock update cycle
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
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