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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*OPTi...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92
***Info:
The OPTi 82C497 is a Direct Mapped Write Back cache controller with
one level write buffer that is an optional part of the DXBB (Building
Block) Chip set. The DXBB also contains the 82C496 and the 82C206,
which form the heart of the system. The 82C497 is added to the DXBB
chip set for cache based systems.
The OPTi 82C496 offers an upgradable CPU module base-board solution
for the 80386 or the 80486 PC/AT system. By swapping the CPU module,
the vendor can configure the 82C496 driven base-board into various
32-bit AT systems - 386 or 486 CPU, with cache or without cache and
rated at 16MHz- 50MHz.
For the Non-Cache systems, the CPU interfaces directly with the 82C496
and the local devices, like the local VGA controller or the local hard
disk adaptor.
For cache based systems the 82C497 (the cache controller) sits between
the CPU and the 82C496 and the local devices. All the high frequency
signals are isolated by the 82C497. This allows the base-board to run
at a fixed speed (25 or 33MHz) - while the CPU and the Cache can run
synchronously at any determined rated speed. This provides a reliable
upgrade method for the CPU modules.
***Configurations:...
***Features:...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
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*VLSI...
*Western Digital...
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91
***Info:
GENERAL DESCRIPTION
The WD76C20 is a member of the WD7600 chip set which provides a
cost-effective, power-efficient solution to PC systems design,
especially those relating to "lap-top" devices. The set includes the
WD76C10, the WD76C20, and the WD76C30 as shown in Figure 1-1. Together
these chips provide all necessary logic to build a fully integrated
system board for several varieties of IBM PC/AT compatibles including
systems using 80286, 80386SX, and 80C286 processors.
As part of this chip set, the WD76C20 provides these integral
functions:
o Bus Interface Logic
o IDE Interface
o Chip Select Logic
o Floppy Disk Controller
o Real Time Clock
o Suspend/Resume Logic
The Floppy Disk Controller (FDC) component provides necessary timing
and signalling between the host processor peripheral bus and a floppy
disk drive through a cable connector.
The Real Time Clock component provides calendar and clock information
for the system.
The IDE Interface controls buffering between the system's AT Bus and
PC/AT compatible IDE drive interface.
The Bus Interface Logic controls buffering of data between the
system's AT Bus and the WD76C20.
The Chip Select Logic section provides decoding for selected chip
functions both within the WD76C20 and on the PC/AT motherboard.
Suspend/Resume Logic provides support for chip set power-down and
resume sequences.
***Versions:...
***Features:...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
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