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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**82C381/382 HiD/386 (386DX) c:89
***Info:
The HiD/386 Chipset, 82C381 and 82C382D, support high integration
implementations of Direct Mapped Cache with 32KB/64KB/128KB Cache for
25 and 33 MHz 386/AT Personal Computers. Combined with the 82C206
Integrated Peripherals Controller, it integrates the 386/AT mother-
board to under 20 devices, plus memory. It is designed to cost reduce
discrete and CHIPS’CS8230 based 82385 Cache 386/AT designs, as well as
boost the performance of these designs to 33 MHz, with >64KB Cache.
The 82681 provides system control logic and data bus conversion logic.
The control logic consists of 386 CPU control logic, AT Bus cycle
control, 387 Numeric Processor control logic, synchronous clock divide
logic and control of the local peripheral bus. The data bus conversion
logic consists of various 8, 16, 32 bit conversions for ROM cycles, AT
bus cycles and memory cycles.
The 820382D performs the Memory Management functions for the HiD/AT
chipset. It is designed to optimize cost of high performance 386/AT
systems with 64KB, l28KB or larger Direct Mapped Cache Memory. It also
implements logic to maintain compatibility in the AT environment . It
provides a Page Interleave backend for main DRAM memory, in order to
improve performance during miss cycles. It also has features for
reducing system cost.
It minimizes Cache Memory cost by allowing the use of slow SRAM; by
supporting single EPROM BIOS configurations; putting DRAM on the local
bus and consequently reducing DRAM speeds by 15ns typically; and by
remapping 256K of DRAM between 640K and 1024K to top of main memory.
It provides a very flexible implementation of paging for the main DRAM
memory. For even bank configurations, it provides 2-way or 4-way
interleaving; for odd banks it provides paging. This provides a
flexible approach to increasing the size of the local memory as
software demands increase, without imposing a penalty on performance.
Finally, memory performance is optimized by shadow RAM techniques for
BIOS ROMs; concatenated pages for multiple hank configurations; paging
for odd banks; and variable page size for larger DRAMs.
System Architecture
The HiD/AT chipset is compatible with the 82C206 Integrated
Peripherals Controller. Consequently, with the 82C206, a very high
integration and very high performance 386/AT can be implemented. A
typical motherboard can be designed with less than 20 devices plus
memory.
For larger AT designs, targeted at file-servers and departmental
computers, designs with 8 or more slots can be supported with external
AT bus drivers.
***Configurations:...
***Features:...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD8110 System controller for 80386DX/486 <11/30/93
***Notes:...
***Info:
1.0 INTRODUCTION
The WD8110/LV System Controllers are designed to provide a high
performance, single chip system controller supporting all 80486SX,
80486DX. 80386SX and 80386DX CPUs in AT bus based Desktop/
Laptop/Notebook/Pen-based systems.
1.1 DOCUMENT SCOPE
This document describes the function and operation of the WD8110/LV
System Controller devices. It includes the description of external
logic necessary for efficient use of these devices. The WD8110/LV is
also referred to in this document as the System Controller.
1.3 WD8110/LV POWER MANAGEMENT
Power Management Control (PMC) is used for powering down the processor
or peripherals and includes processor stop clock, slow clock, auto-
matic processor clock speed switching modes and CAS before RAS slow
refresh. Suspend and resume is supported and low power DRAM is
refreshed while the processor and other power consuming devices are
turned off. The power drain for the core logic and VGA controller is
less than 2 mA in this mode. Power and clock speed may be controlled
by the Keyboard Controller. transparently to the 80386 or 80486.
The System Activity Monitor (SAM) is a transparent feature that
replaces the functions previously performed by software. It senses
when the system has been idle for a previously programmed period at
time and determines a clean break point in which to perform power down
activities such as suspend.
The system controller also supports System Management Interrupt (SMI)
with complete I/O trapping of up to six separate I/O ranges. Each
range has an independent timer which can generate an SMI after a
programmed period of time during which there was no I/0 access to that
range.
1.3.1 Desktop Applications
The WD8110/LV provides a high performance solution with a flexible
memory controller architecture. including support for five banks of
memory. The WD8110/LV can fully support an external look-aside cache
or a combination primary and secondary cache. This feature makes it
particularly suitable for use with cached microprocessors where it
maintains cache coherency via its built-in bus snooping capability. In
addition. the WD8110/LV supports Video Local Bus Interface (VLBI) for
enhanced graphics performance.
The built-in power management features of the WD8110/LV allows a high
performance yet power efficient desk top solution.
1.3.2 Portable Applications
The WD8110LV is an ideal choice because of its advanced power
management features and power saving 3.3 volt operation, which
delivers long battery life in a compact footprint. This makes it a
perfect choice for laptop, notebook, pen-based and palmtop computers.
The five bank memory controller on the WD8110LV provides the user with
great flexibility in the selection of 3.3 volt DRAMs to meet system
memory requirements in low voltage platforms. The WD8110LV memory
controller supports JEDEC standard 3.3 volt DRAM in various
configurations, including the JEIDA standard 88-pin DRAM card.
The WD8ll0/LV can be paired with the appropriate support devices from
Western Digital to deliver the most efficient solution for any
platform. For 5 volt desktop or portable platforms, the WD8l10/LV can
be used with the WD76C20 Peripheral Controller and the WD76C30 I/O
Controller. The WD8110 may also be used with the WD7615 Buffer Manager
device and a generic Super I/O chip to implement a low cost desktop
platform. For 3.3 volt applications, the WD8110LV can be used with the
WD76C20ALV and WD76C30ALV, both of which incorporate level translators
(split rail operation). For subnotebook and palmtop type applications,
WD7625LV buffer manager and WD8120LV Super I/O can be added to the
WD8110LV based solution to achieve a very compact footprint.
The WD8110/LV is a fifth generation system controller device derived
from core chips with proven compatibility and design maturity in
several of the industry's leading desktop and portable platforms.
Designed with the state of the art 0.9 micron high performance CMOS
process. the WD8110/LV family maintains architectural compatibility
with Western Digital's WD7600 and WD7855 systems logic chip sets while
incorporating many additional performance enhancements.
***Configurations:...
***Features:...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
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