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**CS8221 NEW Enhanced AT (NEAT) (82C211/82C212/82C215/82C206) c86
***Info:
The CS8221 PC/AT compatible NEAT CHIPSet is an enhanced, high
performance 4 chip VLSI implementation (including the 82C206 IPC) of
the control logic used on the IBM Personal Computer AT. The flexible
architecture of the NEAT CHIPSet allows it to be used in any 80286
based system.
The CS8221 NEAT CHIPSet provides a complete 286 PC/AT compatible
system, requiring only 24 logic components plus memory devices.
The CS8221 NEAT CHIPSet consists of the 82C211 CPU/Bus controller, the
82C212 Page/interleave and EMS Memory controller. the 82C215
Data/Address buffer and the 82C206 Integrated Peripherals Controller
(IPC).
The NEAT CHIPSet supports the local CPU bus, a 16 bit system memory
bus, and the AT buses as shown in the NEAT System Block Diagram [see
datasheet]. The 82C211 provides synchronization and control signals
for all buses. The 82C211 also provides an independent AT bus clock
and allows for dynamic selection between the processor clock and the
user selectable AT bus clock. Command delays and wait states are
software configurable, providing flexibility for slow or fast peri-
pheral boards.
The 82C212 Page/interleave and EMS Memory controller provides an
interleaved memory sub-system design with page mode operation. It
supports up to 8 MB of on-board DRAM with combinations of 64Kbit,
256Kbit and 1Mbit DRAMs. The processor can operate at 16MHz with
0.5-0.7 wait state memory accesses, using 100 nsec DRAMs. This is
possible through the Page Interleaved memory scheme. The Shadow RAM
feature allows taster execution of code stored in EPROM, by down
loading code from EPROM to RAM. The RAM then shadows the EPROM for
further code execution. In a DOS environment, memory above 1Mb can be
treated as LIM EMS memory.
The 82C215 Data/Address buffer provides the buffering and latching
between the local CPU address bus and the Peripheral address bus. It
also provides buffering between the local CPU data bus and the memory
data bus. The parity bit generation and error detection logic resides
in the 82C215.
The 82C206 Integrated Peripherals Controller is an integral part of
the NEAT CHIPSet. It is described in the 82C206 Integrated Peri-
pherals Controller data book.
System Overview
The CS8221 NEAT CHIPSet is designed for use in 12 to 16 MHz 80286
based systems and provides complete support for the IBM PC/AT
bus. There are four buses supported by the CS8221 NEAT CHIPSet as
shown in Figure 1 [see datasheet]: CPU local bus (A and D), system
memory bus (MA and MD), I/O channel bus (SA and SD), and X bus (XA and
XD). The system memory bus is used to interface the CPU to the DRAMs
and EPROMs controlled by the 82C212. The I/O channel bus refers to
the bus supporting the AT bus adapters which could be either 8 bit or
16 bit devices. The X bus refers to the peripheral bus to which the
82C206 IPC and other peripherals are attached in an IBM PC/AT.
***Configurations:...
***Features:...
**CS8223 LeAPset [no datasheet] ?
**CS8225 CHIPS/250 PS/2 50/60 [no datasheet, some info] c88...
**CS8227 CHIPSlite (82C235/82C641) ?...
**CS8230 386/AT (82C301/302/303/304/305/306)cFeb87...
**CS8231 TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306) c86...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C471/407 Green PC ISA-VLB 486 Single Chip <94
***Info:...
***Configurations:...
***Features:
o Fully IBM PC/AT Compatible. 80486DX2/DX/SX/SL Enhanced, P24D/P24T/
P24C, M6/M7 and Am486DXL/Am486DXL2 Single Chip Controller
o Supports L1 Cache Writeback CPU (P24T/P24D/M6/M7) systems
o Direct Mapped Cache Controller
- Write-Back or Write-Through Schemes
- Bank Interleave or Non-Interleave Cache
- 0/1 Wait State Cache Write Hit
- Flexible Cache Size : 32/64/128/256/512KB or 1MB
- 7 bits or 8 bits TAG addresses
- Flexible 2-1-1-1, 3-1-1-1, 2-2-2-2 and 3-2-2-2 Burst
Read/Write Timing
o Fast Page Burst Mode DRAM Controller
- 4 Banks up to 128MB of DRAMs
- 256K/512K/1M/2M/4M/16MXN DRAM Type
- Programmable DRAM Speed
- Double-sided SIMMs
o Two Programmable Non-Cacheable Regions (64KB-4MB area)
o CAS before RAS Transparent DRAM Refresh
o BIOS/Video ROM Cacheable
o Shadow RAM in Increments of 32KB
- Option to Disable Cache in Shadow RAM Area
o 256K Memory Relocation
o 8042 Emulation of Fast A2OGATE and CPU Reset
o Supports Port 92h
o Hardware/Software De-Turbo Switch
o Supports Two VL-Bus Master
o Supports Flash Memory
o Supports Double/Single frequency input
o CPU Operating frequency 0-100 MHz
o Supports Power Management Mode
- Supports the SMM and the SMI
- CPU Stop Clock Function
- Four Power Saving States
- Long and Short System Timers
- Supports the APM control
- Supports Break Switch control
- Power Saving also on non-SM] CPU
- More System Event Monitoring and the Power Saving Control
o AT Bus State Machine and Controller
o Synchronous/Asynchronous AT Bus Clock
o Programmable AT Bus Speed
- l/2,l/3,1/4,l/5,1/6,1/8,l/10 of Input Clock or 7.159MHz
o Programmable Wait State Generation
- 1 or 2 Wait States for l6-Bit Transfers
- 4 or 5 Wait States for 8-Bit Transfers
o Programmable I/O Recovery Time
o Programmable driving current for the DRAM and the ISA bus signals
o 32-Bit Data Buffer Between CPU and AT System
o Data Conversion and Swapping Logic for 32-/16-/8-Bit Transfers
During CPU and DMA Cycles
o Data Latches for AT Read Cycles
o Parity Generation and Detection Logic
o Port B Register and NMI Logic
o Integrated Peripheral Controllers
- 8259A x2 / 8237x2 / 8254 / 74LS612
o 387/487SX and Weitek 3167/4167 Coprocessors Interface
o 208-Pin PQFP
o 0.8nm Low Power CMOS Technology
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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