[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84
***Notes:...
***Info:
Each 'LS610 and 'LS612 memory mapper integrated circuit contains a
4-line to 16-line decoder, a 16-word by 12-bit RAM, 16 channels of
2-line to 1-line multiplexers, and other miscellaneous circuitry on a
monolithic chip. Each 'LS610 also contains 12 latches with an enable
control.
The memory mappers are designed to expand a microprocessor's memory
addressing capability by eight bits. Four bits of the memory address
bus (see System Block Diagram)[see datasheet] can be used to select
one of 16 map registers that contain 12 bits each. these 12 bits are
presented to the system memory address bus through the map output
buffers along with the unused memory address bits from the CPU.
However, addressable memory space without reloading the map registers
is the same as would be available with the memory mapper left out.
The addressable memory space is increased only by periodically
reloading the map registers from the data bus. This configuration
lends itself to memory utilization of 16 pages of 2^(n-4) registers
each without reloading (n - number of address bits available from
CPU).
These devices have four modes of operation: read, write, map, and
pass. Data may be read from or loaded into the map register selected
by the register select inputs (RS0 thru RS3) under control of R/W
whenever chip select (CS) is low. The data I/O takes place on the data
bus DO thru D7. The map operation will output the contents of the map
register selected by the map address inputs (MA0 thru MA3) when CS is
high and MM (map mode control) is low. The 'LS612 output stages are
transparent in this mode, while the 'LS610 outputs may be transparent
or latched. When CS and MM are both high (pass mode), the address bits
on MA0 thru MA3 appear at M08-MO11, respectively (assuming appropriate
latch control) with low levels in the other bit positions on the map
outputs.
***Versions:...
***Features:...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD7855 System controller for 80386SX <09/25/92
***Notes:...
***Info:
1.3 GENERAL DESCRIPTION
Western Digital's WD7855/LV single chip ISA System Controller is
designed for high-performance IBM PC/AT compatible platforms.
Available for desktop, portable or low voltage (LV) applications, the
WD7855/LV supports the 803868X microprocessor operating at speeds up
to 33 MHz.
The WD7855/LV incorporates seven high-performance system controller
functions which include the ISA bus interface, CPU interface, flexible
memory controller, DMA controller, interrupt controller, timers and
advanced power management. In combination with Western Digital’s
support devices, the WD7855/LV provides a highly flexible and powerful
desktop or portable platform design.
The WD7855/LV is designed to work with all variations of 80386SX
compatible microprocessors. It supports the traditional dynamic CPUs
with the industry's only Processor Power-down feature to minimize
power consumption. The WD7855/LV fully supports static microprocessors
such as the AMD Am386SXL with CPU Stop Clock, System Management
Interrupt and I/O trapping features. The WD7855/LV incorporates
special circuitry which allows for optimizing the cache performance
and maintaining cache coherency with cached CPUs such as the Cyrix
Cx4868LC.
1.3.1 Desktop Applications
The WD7855 provides a high performance solution with a flexible memory
controller architecture, including support for eight banks of two way
interleave memory and EMS 4.0 hardware. The WD7855/LV can fully
support an external look-aside cache or a combination primary and
secondary cache. This feature makes it particularly suitable for use
with cached microprocessors such as Cyrix Cx486SLC where it maintains
cache coherency via its built-in bus snooping capability. In addition,
the WD7855/LV supports Video Local Bus Interface (VLBI) for enhanced
graphics performance.
1.3.2 Portable Applications
The WD7855LV is an ideal choice because of its advanced power
management features and power saving 3.3 volt operation which delivers
long battery life in a compact footprint. This makes it a perfect
choice for laptop, notebook, pen based and palmtop computers.
The eight bank memory controller on the WD7855LV provides the user
with great flexibility in the selection of 3.3 volt DRAMs to meet
system memory requirements in low voltage platforms. The WD7855LV
memory controller supports JEDEC standard 3.3 volt DRAM in various
configurations, including the JEIDA standard 88-pin DRAM card.
The WD7855/LV can be paired with the appropriate support devices from
Western Digital to deliver the most efficient solution for any
platform. For 5 volt desktop or portable platforms, the WD7855LV can
be used with the WD76C20 Peripheral Controller and the WD76C30 I/O
Controller. Alternatively, the WD7855 can be used with the WD7615
Buffer Manager device and a generic Super I/O chip to implement a low
cost desktop platform. For 3.3 volt applications, the WD7855LV can be
used with the WD76C20ALV and WD76C30ALV, both of which incorporate
level translators (split rail operation). For subnotebook and palmtop
type applications, WD7625LV buffer manager can be added to the
WD7855LV based solution to achieve a very compact footprint.
The WD7855/LV is a fourth generation system controller device derived
from core chips with proven compatibility and design maturity in
several of the industry’s leading desktop and portable platforms.
Designed with the state of the art 0.9 micron high performance CMOS
process, the WD7855/LV family maintains architectural compatibility
with Western Digital's WD7600 and WD7700 systems logic chip sets while
incorporating many additional performance enhancements.
***Configurations:...
***Features:...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved