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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96
***Info:...
***Configurations:...
***Features:
o Supports Intel Pentium CPU and other compatible CPU at
66/60/50MHz (external clock speed)
o Supports VGA Shared Memory Architecture
- Direct Memory Accesses
- Shared Memory Area 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M, 4M.
- Built-in 2-Priority Scheme.
o Supports the Pipelined Address Mode of Pentium CPU.
o Integrated Second Level (L2) Cache Controller
- Write Through and Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Supports Pipelined Burst SRAM.
- Supports 256 KBytes to 1 MBytes Cache Sizes.
- Cache Read/Write Cycle of 3-1-1-1 Pipelined Burst SRAM at 66
Mhz and 3-1-1-1-1-1-1-1 at back to back read cycle.
o Integrated DRAM Controller
- Supports 4 RAS lines, the memory size is from 4MBytes up to
512Mbytes.
- Supports 256K/512K/1M/2M/4M/16M x N 70ns FP/EDO DRAM
- Supports 4K Refresh DRAM
- Supports 3V or 5V DRAM.
- Supports Symmetrical and Asymmetrical DRAM.
- Supports 32 bits/64 bits mixed mode configuration
- Supports Concurrent Write Back
- Table-free DRAM Configuration, Auto-detect DRAM size, Bank
Density, Single/Double sided DRAM, EDO/ FP DRAM for each bank
- Supports CAS before RAS "Intelligent Refresh"
- Supports Relocation of System Management Memory
- Programmable CAS# Driving Current
- Fully Configurable for the Characteristic of Shadow RAM (640
KByte to 1 Mbyte)
o Supports EDO/FP 5/6-2-2-2/-3-3-3 Burst Read Cycles
o Two Programmable Non-Cacheable Regions
o Option to Disable Local Memory in Non-Cacheable Regions
o Shadow RAM in Increments of 16 KBytes
o Supports SMM Mode of CPU.
o Supports CPU Stop Clock.
o Supports Break Switch.
o Provides High Performance PCI Arbiter.
- Supports 4 PCI Master.
- Supports Rotating Priority Mechanism.
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Supports Concurrency between CPU to Memory and PCI to PCI.
o Integrated PCI Bridge
- Supports Asynchronous PCI Clock.
- Translates the CPU Cycles into the PCI Bus Cycles
- Provides CPU-to-PCI Read Assembly and Write Disassembly
Mechanism
- Translates Sequential CPU-to-PCI Memory Write Cycles into PCI
Burst Cycles.
- Zero Wait State Burst Cycles.
- Supports Advance Snooping for PCI Master Bursting.
- Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes.
o 388-Pin BGA Package.
o 0.5μm CMOS Technology.
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
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*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD7855 System controller for 80386SX <09/25/92
***Notes:...
***Info:
1.3 GENERAL DESCRIPTION
Western Digital's WD7855/LV single chip ISA System Controller is
designed for high-performance IBM PC/AT compatible platforms.
Available for desktop, portable or low voltage (LV) applications, the
WD7855/LV supports the 803868X microprocessor operating at speeds up
to 33 MHz.
The WD7855/LV incorporates seven high-performance system controller
functions which include the ISA bus interface, CPU interface, flexible
memory controller, DMA controller, interrupt controller, timers and
advanced power management. In combination with Western Digital’s
support devices, the WD7855/LV provides a highly flexible and powerful
desktop or portable platform design.
The WD7855/LV is designed to work with all variations of 80386SX
compatible microprocessors. It supports the traditional dynamic CPUs
with the industry's only Processor Power-down feature to minimize
power consumption. The WD7855/LV fully supports static microprocessors
such as the AMD Am386SXL with CPU Stop Clock, System Management
Interrupt and I/O trapping features. The WD7855/LV incorporates
special circuitry which allows for optimizing the cache performance
and maintaining cache coherency with cached CPUs such as the Cyrix
Cx4868LC.
1.3.1 Desktop Applications
The WD7855 provides a high performance solution with a flexible memory
controller architecture, including support for eight banks of two way
interleave memory and EMS 4.0 hardware. The WD7855/LV can fully
support an external look-aside cache or a combination primary and
secondary cache. This feature makes it particularly suitable for use
with cached microprocessors such as Cyrix Cx486SLC where it maintains
cache coherency via its built-in bus snooping capability. In addition,
the WD7855/LV supports Video Local Bus Interface (VLBI) for enhanced
graphics performance.
1.3.2 Portable Applications
The WD7855LV is an ideal choice because of its advanced power
management features and power saving 3.3 volt operation which delivers
long battery life in a compact footprint. This makes it a perfect
choice for laptop, notebook, pen based and palmtop computers.
The eight bank memory controller on the WD7855LV provides the user
with great flexibility in the selection of 3.3 volt DRAMs to meet
system memory requirements in low voltage platforms. The WD7855LV
memory controller supports JEDEC standard 3.3 volt DRAM in various
configurations, including the JEIDA standard 88-pin DRAM card.
The WD7855/LV can be paired with the appropriate support devices from
Western Digital to deliver the most efficient solution for any
platform. For 5 volt desktop or portable platforms, the WD7855LV can
be used with the WD76C20 Peripheral Controller and the WD76C30 I/O
Controller. Alternatively, the WD7855 can be used with the WD7615
Buffer Manager device and a generic Super I/O chip to implement a low
cost desktop platform. For 3.3 volt applications, the WD7855LV can be
used with the WD76C20ALV and WD76C30ALV, both of which incorporate
level translators (split rail operation). For subnotebook and palmtop
type applications, WD7625LV buffer manager can be added to the
WD7855LV based solution to achieve a very compact footprint.
The WD7855/LV is a fourth generation system controller device derived
from core chips with proven compatibility and design maturity in
several of the industry’s leading desktop and portable platforms.
Designed with the state of the art 0.9 micron high performance CMOS
process, the WD7855/LV family maintains architectural compatibility
with Western Digital's WD7600 and WD7700 systems logic chip sets while
incorporating many additional performance enhancements.
***Configurations:...
***Features:...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
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