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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96
***Info:...
***Configurations:...
***Features:
o Supports Intel Pentium CPU and other compatible CPU at
66/60/50MHz (external clock speed)
o Supports VGA Shared Memory Architecture
- Direct Memory Accesses
- Shared Memory Area 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M, 4M.
- Built-in 2-Priority Scheme.
o Supports the Pipelined Address Mode of Pentium CPU.
o Integrated Second Level (L2) Cache Controller
- Write Through and Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Supports Pipelined Burst SRAM.
- Supports 256 KBytes to 1 MBytes Cache Sizes.
- Cache Read/Write Cycle of 3-1-1-1 Pipelined Burst SRAM at 66
Mhz and 3-1-1-1-1-1-1-1 at back to back read cycle.
o Integrated DRAM Controller
- Supports 4 RAS lines, the memory size is from 4MBytes up to
512Mbytes.
- Supports 256K/512K/1M/2M/4M/16M x N 70ns FP/EDO DRAM
- Supports 4K Refresh DRAM
- Supports 3V or 5V DRAM.
- Supports Symmetrical and Asymmetrical DRAM.
- Supports 32 bits/64 bits mixed mode configuration
- Supports Concurrent Write Back
- Table-free DRAM Configuration, Auto-detect DRAM size, Bank
Density, Single/Double sided DRAM, EDO/ FP DRAM for each bank
- Supports CAS before RAS "Intelligent Refresh"
- Supports Relocation of System Management Memory
- Programmable CAS# Driving Current
- Fully Configurable for the Characteristic of Shadow RAM (640
KByte to 1 Mbyte)
o Supports EDO/FP 5/6-2-2-2/-3-3-3 Burst Read Cycles
o Two Programmable Non-Cacheable Regions
o Option to Disable Local Memory in Non-Cacheable Regions
o Shadow RAM in Increments of 16 KBytes
o Supports SMM Mode of CPU.
o Supports CPU Stop Clock.
o Supports Break Switch.
o Provides High Performance PCI Arbiter.
- Supports 4 PCI Master.
- Supports Rotating Priority Mechanism.
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Supports Concurrency between CPU to Memory and PCI to PCI.
o Integrated PCI Bridge
- Supports Asynchronous PCI Clock.
- Translates the CPU Cycles into the PCI Bus Cycles
- Provides CPU-to-PCI Read Assembly and Write Disassembly
Mechanism
- Translates Sequential CPU-to-PCI Memory Write Cycles into PCI
Burst Cycles.
- Zero Wait State Burst Cycles.
- Supports Advance Snooping for PCI Master Bursting.
- Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes.
o 388-Pin BGA Package.
o 0.5μm CMOS Technology.
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**FE3400/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:86
***Info:...
***Configurations:
FE3400 (Max 10 MHz):
FE3000A
FE3010 (Max 10 MHz)
FE3020
FE3030
This chip list is based on the FE3010 datasheet. This datasheet does
not state it is part of the FE3400 chip set. However it corresponds
with the chip list given for the FE3400B.
FE3400B (Max 12 MHz): <88
FE3000A *1
FE3010B,*1
FE3020
FE3030
>* Note datasheet i have for this part states MAX 10 MHz, which
conflicts with the FE3400B definition.
***Features:...
**FE3500/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:87...
**FE3600/A/B/C 16/20MHz AT Chip set c:88...
**FE5300 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE5400 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE6500 CPU Core Logic for PS/2 Model 70/80 Compatibles c:88...
**WD6400SX/LP CPU Core Logic for PS/2 386SX Compatibles <90...
**WD6500 CPU Core Logic for PS/2 386DX/486 Compatible <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX <11/25/91...
**WD7700/LP System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855 System controller for 80386SX <09/25/92...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
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