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*AMD . . . . . . . [no datasheets, some info]...
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*Contaq . . . . . [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C546/547 Python PTM3V c:94
***Notes:...
***Info:
The OPTi Python Chipset provides a highly integrated solution for
fully compatible, high-performance PC/AT platforms. Together, with
OPTi's 82C206 Integrated Peripheral Controller (IPC), this chipset
will support the Pentium processor in the most cost effective and
feature-rich designs available today. This highly integrated approach
provides the foundation for a cost effective platform without
compromising performance. The OPTi Python Chipset supplies a powerful
solution positioned to deliver value without neglecting quality,
compatibility, or reliability.
The Python Chipset is comprised of two chips, the 82C547 System
Controller (SYSC) and the 82C546 AT Bus Controller (ATC). A complete
Pentium processor solution consists of the Python Chipset and the
82C206 Integrated Peripheral Controller (IPC).
82C546 (ATC) AT Bus Controller
The 82C546 ATC integrates the AT bus interface and data buffers for
transfers between the CPU data bus, local data bus and the DRAM data
bus. It also provides the ISA to local bus command translation.
o 208-pin PQFP
o Data bus buffer (host data to memory data)
o Data bus buffer control (ISA to memory)
o Parity generation and detection circuitry
o Keyboard controller chip select
o Local bus interface (ISA to local bus command translation)
82C547 (SYSC) System Controller
The 82C547 SYSC provides the control functions for the host CPU
interface, the 32-bit local bus interface, the 64-bit Level 2 (12)
cache and the 64-bit DRAM bus. The SYSC also controls the data flow
between the CPU bus, the DRAM bus, the local bus, and the 8/16-bit ISA
bus.
o 160-pin PQFP
o Pentium CPU interface
o DRAM controller
o L2 cache controller
o Ll cache controller
o Local bus interface
o Reset generation
o Arbitration logic
o Data bus buffer control (memory data to/from host data)
o Extended DMA page register
o Keyboard emulation of A20M# and CPU warm reset
o Port B and Port 92h Register
82C206 (IPC) Integrated Peripherals Controller
The 82C206 IPC provides two DMA controllers, two interrupt control-
lers, one timer/counter, and a real-time clock in an industry standard
single-chip solution for the peripherals attached to the PC/AT
peripheral bus.
o 84-pin PLCC or 100-pin PQFP
o Supports four DMA transfer modes
o Special Commands provided for ease of programming
Support Chips
The 82C606A and 82C606B are two buffer/translation devices used to
translate 3.3V signals to 5.0V signal levels in Python motherboard
solutions. These devices buffer the CPU address bus to the ISA and VL
address buses, the 82C546 ATC's memory data bus to the ISA data bus,
the peripheral XD bus to the ISA SA and SD buses. The 82C606A and
82C606B integrate a number of glue logic TTL devices (approximately
eleven), hence reducing the amount of TTL on the motherboard. The
82C606A and 82C606B devices are actually the same device with two
strapping options. Pulling the CONFI/2# pin high causes the device to
function in the 82C606A Mode. Pulling the CONFII2# pin low configures
the device to function in the 82C606B Mode of operation.
o 100-pin PQFP
o Mixed voltage to support 3.3V to 5.0V signal translation
o Two devices replace approximately eleven TTL devices
***Configurations:...
***Features:...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C110 Combination I/O chip ?
***Info:
The VL82C110 Combination I/O chip replaces several of the commonly
used peripherals found in PC/AT-compatible computers. The VL82C110
contains a 765A compatible floppy disk controller with a digital data
clock separator, writ precompensation logic and the necessary control
registers. It also contains two 16C450 compatible UARTs, a Centronics
compatible printer port, and an internal PMU (power management unit)
which is useful in applications where low power consumption is
essential. Additionally, a PLL clock circuit is included to provide
one of seven of the commonly used CPU clock frequencies. This 100-pin
chip allows designers to implement a very cost-effective, minimum chip
count motherboard containing functions that are common to virtually
all PCs.
The internal PMU provides a Sleep output which OS asserted via
automatically after a programmable time delay period of inactivity in
any of the major on-chip functions. Conversely, the sleep output will
be de-asserted when any activity is detected to any of the major
on-chip functions.
The on-chip UARTs are 100% software compatible with the VL16C450 ACE.
The bidirectional parallel port provides a PS/2 software compatible
interface between a Centronics-style printer and the VL82C110. Direct
drive is provided so that all that is necessary to interface to the
line printer is a resistor-capacitor network. The bidirectional
feature (option) is software programmable for backwards PC/AT-
compatibility.
The on-chip disk controller OS 100% compatible to the industry
standard 765A. The internal digital data separator is capable of
operating up to a 500 kb/s data rate. The Controller also implements
all of the DP8473 disk controller functions.
The necessary signals are provided to implement the Integrated Drive
Electronics (IDE) interface.
A 24 MHz oscillator is included for UART baud rate generation and the
floppy disk controller clock, It is also used to generate, via
software control, a 20, 25, 32, 40, 50, 66 or 80 MHz output which can
be used as a CPU input clock. This feature may be disabled at power-up
reset time.
Software configurable registers are provided to enable and disable
major blocks, assign addresses, and control other functions within the
VL82C110.
***Versions:...
***Features:...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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