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**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION

The  82489DX  Advanced   Programmable  Interrupt  Controller  provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.

The main  function of the  82489DX is to provide  interrupt management
across all  processors. This  dynamic interrupt  distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in  systems with multiple  I/O subsystems, where  each subsystem
can  have  its  own  set  of  interrupts.   This  chip  also  provides
inter-processor interrupts,  allowing any  processor to  interrupt any
processor or set  of processor. Each 82489DX I/O  init interrupt input
pin is individually  programmable by software as either  edge or level
triggered.  The interrupt vector and interrupt steering information an
be specified  per pin.  A  32-bit wide timer  is provided that  can be
programmed to interrupt the local processor.  the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate  time slice interrupts locally to  that processor.  the
82489DX   provides   32-bit   software    access   to   its   internal
registers. Since no  82489DX register read have any  side effects, the
82489DX registers  can be aliased  to a  user read-only page  for fast
user access (e.g., performance monitoring timers).

The 82489DX  supports a generalized naming/addressing  scheme that can
be tailored by  software to fit a variety of  system architectures and
usage  models.   It  also  supports 8259A  compatibility  by  becoming
virtually  transparent with  regard to  an externally  connected 8259A
style controller, making the 8259A visible to software.

***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**VL82C110 Combination I/O chip                                      ?
***Info:...
***Versions:...
***Features:
o   Combines the functions of the following PC/AT compatible 
    peripheral chips:
    - Two 16C450 UARTs
    - Parallel printer port
    - 765A compatible floppy disk controller with digital data clock 
      separator
o   Serial ports 100% National NS16C450 compatible
o   UARTs can be programmed as COM1-COM4
o   Bidirectional line printer port
o   CMOS direct drive of Centronics-style interface
o   Printer Port can be programmed as LPT2, 3
o   IDE bus control signals included
o   24 mA bus interface drivers
o   48 mA floppy drive interface
o   Single 24 MHz crystal/oscillator
o   Internal PMU (power management unit)
o   PLL clock circuit for one of seven CPU clock frequencies
o   Pin compatible with National PC87310
o   Hard disk select logic
o   Single 100-lead plastic quad flat pack


**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
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