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**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
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**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91
***Info:
The SL82C465 cache controller supports both 1X and 2X clock modes. The
1X clock  mode means that the CCLK2  signal is used as  the CPU clock;
the 2X clock  mode means that the PCLK signal  (half the frequency and
the phase indicator  of CCLK2) is used as the  CPU clock. The SL82C465
and other CPU local bus devices run at the same clock frequency as the
CPU, while  the rest of the system  runs at the frequency  of PCLK. In
other words, the operating frequency of the system logic is either the
same (2X clock mode) or half the speed of the CPU (1X clock mode). For
the 1X clock mode, the timing of the signals between the CPU/Cache and
the system logic interface  is converted by the SL82C465 automatically
to  satisfy  the requirement  of  individual  clocks.  Table 1-1  [see
datasheet] lists  the operating frequencies  of the CPU local  bus and
the system logic with the oscillator used.

The 2X  clock mode is recommended  for a CPU frequency  no faster than
33Mhz because the system logic  is available at the targeted speed and
the  performance  is  slightly  better  than if  1X  clock  mode  were
used. For  a CPU  frequency faster  than 33Mhz, the  1X clock  mode is
preferred  for  486  systems  because  it  becomes  increasingly  more
difficult to  build a reliable  system with an oscillator  faster than
66Mhz.

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*TI (Texas Instruments)...
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*VIA...
*VLSI...
**VL82C108 TOPCAT Combination I/O chip                               ?
***Info:
The VL82C108 Combo  chip replaces with a single  100-pin chip, several
of   the   commonly  used   peripherals   found  in   PC/AT-compatible
computers. This  chip, when used with VLSI  PC/AT-compatible chip set,
allows designers to implement a very cost-effective minimum chip count
motherboard containing functions that are common to virtually all PCs.

The on-chip UART  is completely software compatible  with the VL16C450
ACE.

The bidirectional  parallel port  provides a PS/2  software compatible
interface between  a Centronics-type printer and  the VL82C108. Direct
drive is provided so that all  that is needed to interface to the line
printer is  a resistor/  capacitor network. the  bidirectional feature
(option) is software programmable for backwards PC/AT-compatibility.

The  keyboard/mouse  controller  is  selectable  as  PC/AT-  or  PS/2-
compatible.

Included  is  the control  logic  necessary  for  the support  of  the
Integrated Drive Electronics (IDE) hard  disk bus interface. Hard disk
drives which support the IDE interface often refer to the interface as
"AT Bus" compatible or "Embedded AT Bus" compatible.

The  Combo I/O  chip also  includes  selectable chip  selects for  the
internal  UART and  printer port,  and  four fixed  chip selected  for
external floppy and hard disk controllers.

***Versions:...
***Features:...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
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**Other:...
**Not sure if they actually exist...
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