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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:
o   50 MHz Intel486 DX CPU 
    - RISC Integer Core with Frequent Instructions Executing in One 
      Clock
    - 160 Mbyte/Sec Burst Bus
    - 41 Dhrystone MIPs
    - 11.5M Double Precision Whetstones/Sec.
    - On-Chip Cache and FPU
o   Highly Flexible
    - Supports 128 Kbyte and 256 Kbyte Configurations
    - Complete MESI Protocol Support
    - 32- or 64-Bit Memory Bus Width
    - Synchronous, Asynchronous, and Strobed Memory Bus Protocols
    - Variable Cache Line Sizes and Sectoring
    - Cache Data Parity Option
o   High Performance Second Level Cache
    - Two-Way Set Associative
    - Write-Back or Write Through Cache
    - Zero Wait State Cache Access
    - Concurrent CPU Bus, Memory Bus, and Internal Array Operation
o   Full Multiprocessing Support
    - Implements MESI Write-Back Cache Protocol
    - Low Bus Utilization
    - Automatically Maintains 1st Level Cache Consistency
    - Supports Read-for-Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**VL82C106 Combination I/O chip                                      ?
***Info:...
***Versions:...
***Features:
o   Combines the following PC/AT peripheral chips:
    VL16C450B UART        - COM 1:
    VL16C450B UART        - COM 2:
    Parallel printer port - LPT 1:
    Keyboard/mouse ctrl.  - KBD
    Real-time clock       - RTC
o   Serial ports 100% 16C450B-compatible
o   Bidirectional Line Printer Port (LPT)
o   CMOS direct drive of Centronics type parallel interface
o   PC/AT- or PS/2-compatible keyboard and mouse controller
o   146818A-compatible real-time clock (RTC)
o   16 bytes of additional standby RAM (66 bytes total)
o   IDE bus control signals included (two external 74LS245 and one 
    74LS244, or equivalent, buffers are required)
o   Seven battery-backed programmable chip select registers for auto-
    configuration
o   Preprogrammed default chip select registers
o   Programmable wait state generation
o   5 uA standby current for RTC, RAM and chip select registers
o   Single 128-lead plastic quad flatpack


**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
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**Not sure if they actually exist...
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