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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98...
***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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*Unresearched:...
*VIA...
*VLSI...
**VL82C594/596/597 Wildcat                                         c95
***Notes:...
***Info:
Wildcat is  a 586-class PCI  chipset comprised of the  VL82C594 System
Controller, two  VL82C595 Data Buffers, and  the VL82C596/VL82C597 ISA
Bridge. The VL82C596 is for single processor systems using a P5, P54C,
P54CS, P55C,  K5, or M1 CPU.  The VL82C597 includes the  Intel IO APIC
for use  in Intel-based dual processor systems.  The VL82C594 supports
up to 1G of  fast page mode or EDO DRAM. It also  supports up to 1M of
async,  sync, or  PBSRAM.  The  VL82C595 data  buffers  work with  the
VL82C594  to  provide 3smart2  write  buffering  to yield  exceptional
performance with  or without an L2  cache. The VL82C596/597  acts as a
PCI-ISA bridge and incorporates advanced power management features and
a Real-Time Clock with integrated write protection.

***Configurations:...
***Features:...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
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**Other:...
**Not sure if they actually exist...
*Western Digital...
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