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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in  the configurations section  has been sourced  from the
second.

Difference to 82497/492 is this supports 1 Mbyte to 2 Mbyte cache.

***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98...
***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**VL82C425         486 Cache controller                              ?
***Info:...
***Versions:...
***Features:
o   Single chip second-level cache controller optimized for use with 
    the VL82C486 System Controller
o   Look-aside architecture allows cache to be board-level option
o   Write-back architecture for increased write performance
o   Direct Map with external TAGs
o   Up to 33Mhz operation
o   Supports single motherboard designs for the following cache sizes:
    - 64 KB  (caches 8 or 16 MB DRAM)
    - 128 KB (caches 16 or 32 MB DRAM)
    - 256 KB (caches 32 or 64 MB DRAM)
    - 512 KB (caches 64 or 128 MB DRAM)
    - 1 MB   (caches 128 or 256 MB DRAM)
o   Low total cache system cost:
    - Uses commodity SRAMs for Cache Tag and Cache Data
    - 25 ns data SRAMs; 20 ns tag SRAMs at 33 MHz
o   High Performance:
    - 2-1-1-1 Burst Mode read cycles with two banks of data SRAM
    - 2-2-2-2 Burst Mode read cycles with now bank of data SRAM
    - One wait state writes on cache-hits
    - Minimum cache-miss penalty
o   Flexibility:
    - Supports 8-bit or 9-bit TAG RAM (inclusive of DIRTY bit)
    - Supports one or two banks of SRAM
o   Maintains full coherency during DMA/Master Mode Cycles
    - The VL82C425 is transparent to software, acting as a front-end 
      to system DRAM
o   Setup/sizing mode provides direct access to cache SRAMs
o   128-lead metric quad flat pack (MQFP)

**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
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