[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C546/547 Python PTM3V c:94
***Notes:...
***Info:
The OPTi Python Chipset provides a highly integrated solution for
fully compatible, high-performance PC/AT platforms. Together, with
OPTi's 82C206 Integrated Peripheral Controller (IPC), this chipset
will support the Pentium processor in the most cost effective and
feature-rich designs available today. This highly integrated approach
provides the foundation for a cost effective platform without
compromising performance. The OPTi Python Chipset supplies a powerful
solution positioned to deliver value without neglecting quality,
compatibility, or reliability.
The Python Chipset is comprised of two chips, the 82C547 System
Controller (SYSC) and the 82C546 AT Bus Controller (ATC). A complete
Pentium processor solution consists of the Python Chipset and the
82C206 Integrated Peripheral Controller (IPC).
82C546 (ATC) AT Bus Controller
The 82C546 ATC integrates the AT bus interface and data buffers for
transfers between the CPU data bus, local data bus and the DRAM data
bus. It also provides the ISA to local bus command translation.
o 208-pin PQFP
o Data bus buffer (host data to memory data)
o Data bus buffer control (ISA to memory)
o Parity generation and detection circuitry
o Keyboard controller chip select
o Local bus interface (ISA to local bus command translation)
82C547 (SYSC) System Controller
The 82C547 SYSC provides the control functions for the host CPU
interface, the 32-bit local bus interface, the 64-bit Level 2 (12)
cache and the 64-bit DRAM bus. The SYSC also controls the data flow
between the CPU bus, the DRAM bus, the local bus, and the 8/16-bit ISA
bus.
o 160-pin PQFP
o Pentium CPU interface
o DRAM controller
o L2 cache controller
o Ll cache controller
o Local bus interface
o Reset generation
o Arbitration logic
o Data bus buffer control (memory data to/from host data)
o Extended DMA page register
o Keyboard emulation of A20M# and CPU warm reset
o Port B and Port 92h Register
82C206 (IPC) Integrated Peripherals Controller
The 82C206 IPC provides two DMA controllers, two interrupt control-
lers, one timer/counter, and a real-time clock in an industry standard
single-chip solution for the peripherals attached to the PC/AT
peripheral bus.
o 84-pin PLCC or 100-pin PQFP
o Supports four DMA transfer modes
o Special Commands provided for ease of programming
Support Chips
The 82C606A and 82C606B are two buffer/translation devices used to
translate 3.3V signals to 5.0V signal levels in Python motherboard
solutions. These devices buffer the CPU address bus to the ISA and VL
address buses, the 82C546 ATC's memory data bus to the ISA data bus,
the peripheral XD bus to the ISA SA and SD buses. The 82C606A and
82C606B integrate a number of glue logic TTL devices (approximately
eleven), hence reducing the amount of TTL on the motherboard. The
82C606A and 82C606B devices are actually the same device with two
strapping options. Pulling the CONFI/2# pin high causes the device to
function in the 82C606A Mode. Pulling the CONFII2# pin low configures
the device to function in the 82C606B Mode of operation.
o 100-pin PQFP
o Mixed voltage to support 3.3V to 5.0V signal translation
o Two devices replace approximately eleven TTL devices
***Configurations:...
***Features:...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C480 System/Cache/ISA bus Controller ?
***Info:
The VL82C480 controller is designed to control 486DX or
486SX/487SX-based ISA bus systems operating at up to 40 MHz. It
replaces the following devices on the motherboard:
o Two 82C37A DMA controllers
o Two 82C59A interrupt controllers
o 82C54 timer
o 74LS612 memory mapper
o 82284 clock generator and ready interface
o 82288 bus controller
The following controller blocks are also included on-chip:
o Memory/refresh controller
o Port B and NMI logic
o Bus steering logic
o Turbo Mode control logic
o Parity checking logic
o Parity generation logic
o Writ-back look-aside cache controller
The VL82C480 supports the Weitek 4167 Numeric Coprocessor.
The memory controller logic is capable of accessing up to 64 MB. there
can be up to four banks of 256K, 1M, or 4M DRAMs used in a system. The
VL82C480 can drive two banks without external buffering. Built-in Page
Mode operation and up to two-way interleaving allows the PC designer
to maximize system perform- ance using low-cost DRAMs. Programmable
DRAM timing is provided for RAS# pre- charge, RAs-to-CAS delay, and
CAS# pulse width.
The VL82C480 write-back cache controller logic supports one or two
bank direct map write-back cache with external tag storage. The cache
controller can per- form 2-1-1-1 reads with two banks or 2-2-2-2 reads
with one bank. The VL82C480 can perform one wait state writes on
cache-hits. An optional zero wait state write mode is provided for use
with fast cache SRAMs. The cachable DRAM range includes 2 MB up to 64
MB utilizing cache data SRAM sizes of 32 KB through 1 MB,
respectively.
Shadowing features are supported on 16K boundarys between A0000h and
FFFFFh (640 KB to 1 MB). simultaneous use of shadowed ROM and direct
system board access is possible in a non-overlapping fashion throu-
ghout this memory space. Control over four access options is provided:
1. Access ROM or slot bus for reads and writes.
2. Access system board DRAM for reads and writes.
3. Access system board DRAM for reads and slot bus for writes.
4. Shadow setup mode. Read ROM of slot bus, write system board DRAM.
Three special programmable address regions are provided. the Fast Bus
Clock Reg- ion allows accesses to certain memory regions at a faster
ISA bus clock rate for fat on-board or off-board devices. A
Non-Cacheable Region and/or a Write-Pro- tected Region may be defined
by a set of six registers that allow memory in the region 640 KB to 1
MB to be marked as non-cacheable and/or write-protected in increments
of 16 KB. A further set of registers allows a memory range anywhere in
the first 64 MB of memory to be marked as a DRAM region, an ISA bus
region, or a local bus region, either cachable or non-cacheable in
increments of 2 KB. 64 KB, or 1 MB.
further support for devices that reside on the local bus is provided
through use of the LBA# (Local Bus Access) input, which deselects the
VL82C480 during CPU cycles. Also, a memory range anywhere in the first
64 MB of memory can be pro- grammed via the internal mapping registers
to make the VL82C480 access a local bus device as a CPU bus memory
device during DMA or Master Mode transfers, and de- select the
VL82C480 during CPU cycles.
The VL82C480 handles system board refresh directly ans also controls
the timing of slot bus refresh. Refresh may be performed in
synchronous, Asynchronous or De- coupled Mode. In the Synchronous
Mode, slot bus and on-board DRAM refresh cycles proceed simultaneously
with all memory cycles held until both have completed. The
Asynchronous Mode allows in- and off-board refreshes to be initiated
sumultane- ously, but to complete asynchronously, allowing earlier
access to DRAM. In the Decoupled Mode, a separate refresh counter is
used for slot bus refresh, allowing on-board DRAM and system refreshes
to proceed independently, with DRAM refreshes initiated during bus
idle cycles. CAS-before-RAS refresh is also supported. Re- freshes are
staggered to minimize power supply loading and attenuate noise on the
VDD and VSS pins. The VL82C480 supports the ISA bus standard refresh
period of 15.625 us as well as 125 us.
The interrupt controller logic consists of two 82C50A megacells with
eight inter- rupt request lines each. The two megacells are cascaded
internally and three of the interrupt request inputs are connected to
internal circuitry, sa a total of 13 external interrupt request lines
are available. these 13 interrupt request lines plus the Weitek
interrupt request line, the ten-channel check line, and the Turbo/
Non-Turbo line are scanned in through one pin on the VL82C480. Two
external 74LS166s are required for scanning in these 16 signals.
The interval timer includes one 82C54 counter/timer megacell. the
counter/timer has three independent 16-bit counters and six
programmable counter modes.
The two DMA controllers are 82C37A compatible. Each controls data
transfers bet- ween an I/O channel and on- or off-board memory. The
DMA controllers can transfer data over the full 64 MB range
available. Internal latches are provided for latc- hing the middle
address bits output by the 82C37A megacells on the data bus. The
74LS612 memory mappers are integrated to generate the upper address
bits.
The VL82C480 can be programmed for asynchronous or synchronous
operation of the ISA bus.
The VL82C480 also performs all the data buffer control functions
required for a 486-based ISA bus system. Under the control of the CPU,
the VL82C480 routes data to and from the CPU's D bus, the internal XD
bus, and the slots (SD bus). During CPU ISA bus reads, the data is
latched for synchronization with the CPU. Parity is checked for D bus
DRAM read operations. The chip does not generate parity for CPU writes
to DRAM, but does generate cache write-back cycles. Even parity is
gen- erated and checked.
***Configurations:...
***Features:...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved