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**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90
***Info:
The OPTi-386WB is a highly integrated PC/AT VLSI chipset, for the high
end 386-based AT systems. It includes System Controller (SYSC,
82C391), Data Buffer Controller (DBC, 82C392) and Integrated
Peripheral Controller (82C206). It is designed for system running from
25 Mhz, 33 Mhz and up to 40 Mhz.
SYSC integrates the write-back cache controller, local DRAM control
logic AT bus and CPU interface circuitry. DBC includes the data
buffers, AT bus control, decoding logic for keyboard controller, reset
and clock generation logic.
A high performance 386-based system can be implemented easily with 386
WB PC/AT chipset.
***Configurations:...
***Features:...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C480 System/Cache/ISA bus Controller ?
***Info:...
***Configurations:...
***Features:
o Fully compatible with 486-based ISA bus systems
o Power-on reset option selects various operational modes
o Up to 40 MHz CPU operation
o Replaces the following peripheral logic on the motherboard:
- Two 82C37A DMA controllers
- 74LS612 memory mappers (extended to support 64 MB)
- Two 82C59A interrupt controllers
- 82C54 timer
- 82284 clock generator and ready interface
- 82288 bus controller
o Memory controller features include:
- Up to 64 MB system memory
- 256K, 1M or 4M DRAM
- Double-sided SIMMs
- Page Mode DRAM access
- Two-way interleave support
- Programmable RAS#/CAS# timing
- Burst read and write support
- Parity generation/checking for on-board DRAM
- Staggered RAS# refresh
o Supports:
- One to four banks 32 bits wide
- 8- or 16-bit wide BIOS ROM
- shadow RAM in the 640K-1M area
- Asynchronous ISA bus operation up to 16 MHz
- Relocation of slot ROMs
- Access to devices residing on the local bus
- Weitek 4167 numeric coprocessor
o 0.8-micron CMOS technology
o 208-lead MQFP (metric quad flat pack)
o Includes:
- Memory/refresh controller
- Port A, B, and NMI logic
- Bus steering logic
- Turbo control
- hidden refresh
- Three-stateable outputs for board testing
o Selectable slow DRAM refresh saves power
o On-chip write-back cache controller:
- External tags
- Direct map
- Separate "dirty" RAM not required
- 2-1-1-1 reads with two banks, 2-2-2-2 with one bank
- 32 KB to 1MB cache size
- One wait state writes on cache-hits
- Optional zero wait state writes
- Optional one wait state reads
o Other features:
- Programmable for 10- or 16-bit internal I/O addressing
- Programmable drive on the DRAM and ISA bus signals
- Programmable memory access to define "fast-bus", local bus, slot
bus, non-cacheable and write-protect areas
- Input pin defines access to local bus devices
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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