[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90, 815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich desktops. The high-speed interconnect between the CPU
and cache components has been optimized to provide zero-wait state
operation. This CPU Cache chip set is fully compatible with existing
software, and has new data integrity features for mission critical
applications.
The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82498 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit wide memory bus widths, 32-, and 64-byte line sizes, and
optional sectoring. The data path between the CPU bus and memory bus
is separated by the 82493, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C325 VL82C386SX System Cache controller ?
***Info:...
***Versions:...
***Features:
o Optimized for TOPCAT 386SX and SCAMP-LT chip sets
o Improved i386SX and AMD386SX system performance:
- Fast look-aside architecture
- Zero wait state read-hit access
- Reduces average processor wait states to near zero
o Multiple cache organizations
- Two-way set associative: 16KB
- Two-way set associative: 32KB
o Memory update strategy
- Write-thru
o Least recently used (LRU) replacement algorithm
o Integrates complete cache directory on-chip
o Supports memory configurations to 16 MB
o Programmable cache architecture
- Block size: 8 or 16 bytes
- Line size: 2 bytes
- Update strategies: single cycle (one line)
o Write-protect region support
- Write-protect regions (#): 256
- Write-protect region size: 2KB between 512K and 1M
o Non-cacheable region support
- Non-cache regions (#): 504
- Non-cacheable region size:
64KB below 512K
2KB between 512K and 1M
64KB above 1M
o 25 MHz operation
o Optimized for one or two dual 4K x8 cache data RAMs
o Operates both in pipelined and in non-pipelined modes
o Built-in self-test and cache data RAM testability features
o Auto-flush on EMS-update events
o 100-lead MQFP
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved