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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96
***Info:...
***Configurations:...
***Features:
o Supports Intel Pentium CPU and other compatible CPU at
66/60/50MHz (external clock speed)
o Supports VGA Shared Memory Architecture
- Direct Memory Accesses
- Shared Memory Area 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M, 4M.
- Built-in 2-Priority Scheme.
o Supports the Pipelined Address Mode of Pentium CPU.
o Integrated Second Level (L2) Cache Controller
- Write Through and Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Supports Pipelined Burst SRAM.
- Supports 256 KBytes to 1 MBytes Cache Sizes.
- Cache Read/Write Cycle of 3-1-1-1 Pipelined Burst SRAM at 66
Mhz and 3-1-1-1-1-1-1-1 at back to back read cycle.
o Integrated DRAM Controller
- Supports 4 RAS lines, the memory size is from 4MBytes up to
512Mbytes.
- Supports 256K/512K/1M/2M/4M/16M x N 70ns FP/EDO DRAM
- Supports 4K Refresh DRAM
- Supports 3V or 5V DRAM.
- Supports Symmetrical and Asymmetrical DRAM.
- Supports 32 bits/64 bits mixed mode configuration
- Supports Concurrent Write Back
- Table-free DRAM Configuration, Auto-detect DRAM size, Bank
Density, Single/Double sided DRAM, EDO/ FP DRAM for each bank
- Supports CAS before RAS "Intelligent Refresh"
- Supports Relocation of System Management Memory
- Programmable CAS# Driving Current
- Fully Configurable for the Characteristic of Shadow RAM (640
KByte to 1 Mbyte)
o Supports EDO/FP 5/6-2-2-2/-3-3-3 Burst Read Cycles
o Two Programmable Non-Cacheable Regions
o Option to Disable Local Memory in Non-Cacheable Regions
o Shadow RAM in Increments of 16 KBytes
o Supports SMM Mode of CPU.
o Supports CPU Stop Clock.
o Supports Break Switch.
o Provides High Performance PCI Arbiter.
- Supports 4 PCI Master.
- Supports Rotating Priority Mechanism.
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Supports Concurrency between CPU to Memory and PCI to PCI.
o Integrated PCI Bridge
- Supports Asynchronous PCI Clock.
- Translates the CPU Cycles into the PCI Bus Cycles
- Provides CPU-to-PCI Read Assembly and Write Disassembly
Mechanism
- Translates Sequential CPU-to-PCI Memory Write Cycles into PCI
Burst Cycles.
- Zero Wait State Burst Cycles.
- Supports Advance Snooping for PCI Master Bursting.
- Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes.
o 388-Pin BGA Package.
o 0.5μm CMOS Technology.
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
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*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97
***Info:
The VT82C596 MPIPC (Mobile PCI Integrated Peripheral Controller) is a
high integration, high performance, power-efficient, and high
compatibility device that supports Intel and non-Intel based processor
to PCI bus bridge functionality to make a complete Microsoft
PC97-compliant PCI/ISA system. In addition to complete ISA extension
bus functionality, the VT82C596 includes standard intelligent
peripheral controllers:
a) Master mode enhanced IDE controller with dual channel DMA engine
and interlaced dual channel commands. Dedicated FIFO coupled with
scatter and gather master mode operation allows high performance
transfers between PCI and IDE devices. In addition to standard PIO and
DMA mode operation, the VT82C596 also supports the UltraDMA-33
standard to allow reliable data transfer rates up to 33MB/sec
throughput. The IDE controller is SFF-8038i v1.0 and Microsoft
Windows- 95 compliant.
b) Universal Serial Bus controller that is USB v1.0 and Universal HCI
v1.1 compliant. The VT82C596 includes the root hub with two function
ports with integrated physical layer transceivers. The USB controller
allows hot plug and play and isochronous peripherals to be inserted
into the system with universal driver support. The controller also
implements legacy keyboard and mouse support so that legacy software
can run transparently in a non-USB-aware operating system environment.
c) Keyboard controller with PS2 mouse support.
d) Real Time Clock with 256 byte extended CMOS. In addition to the
standard ISA RTC functionality, the integrated RTC also includes the
date alarm, century field, and other enhancements for compatibility
with the ACPI standard.
e) Notebook-class power management functionality compliant with ACPI
and legacy APM requirements. Multiple sleep states (power-on suspend,
suspend-to-DRAM, and suspend-to-Disk) are supported with hardware
automatic wake-up. Additional functionality includes event
monitoring, CPU clock throttling and stop (Intel processor protocol),
PCI bus clock stop control, modular power, clock and leakage control,
hardware-based and software-based event handling, general purpose I/O,
chip select and external SMI.
f) Full System Management Bus (SMBus) interface.
g) Distributed DMA capability for support of ISA legacy DMA over the
PCI bus. PC/PCI and Serial IRQ mechanisms are also supported for
docking and non-docking applications.
h) Plug and Play controller that allows complete steerability of all
PCI interrupts to any interrupt channel. Three additional steerable
interrupt channels are provided to allow plug and play and
reconfigurability of on-board peripherals for Windows 95 compliance.
i) External IOAPIC interface for Intel-compliant symmetrical multi-
processor systems.
The VT82C596 also enhances the functionality of the standard ISA
peripherals. The integrated interrupt controller supports both edge
and level triggered interrupts channel by channel. The integrated DMA
controller supports type F DMA in addition to standard ISA DMA
modes. Compliant with the PCI-2.1 specification, the VT82C596 supports
delayed transactions so that slower ISA peripherals do not block the
traffic of the PCI bus. Special circuitry is built in to allow
concurrent operation without causing dead lock even in a PCI-to-PCI
bridge environment. The chip also includes eight levels (doublewords)
of line buffers from the PCI bus to the ISA bus to further enhance
overall system performance.
***Versions:...
***Features:...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
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