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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?
***Configurations:...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94
***Info:...
***Versions:...
***Features:
o   VL to PCI Bridge
    - Combined with VT82C486 or VT82C496G for 80486SX/DX/DX2/DX4 based 
      PCI/VL/ISA Green-PC systems
    - Combined with VT82C530MV chip set for Pentium/P54C/M1 based 
      PCI/VL/ISA Green-PC Systems
o   Sophisticated Bridging Capabilities
    - Supports PCI master to PCI slave cycles
    - Supports PCI master to VL bus slave, system memory and ISA 
      slave cycles
    - Supports VL master including CPU to PCI slave cycles
    - Supports ISA master to VL or PCI slave cycles
    - Supports multiple accelerated decoding schemes from VL master 
      including CPU to PCI and ISA slaves
    - Supports CPUs with write-back level-one cache
    - Concurrent CPU and PCI operation
    - 4 level of CPU/VL to PCI post write buffers
    - Automatic detection of data streaming burst cycles from CPU/VL 
      to PCI bus
    - 4 level of post write buffers from PCI master to VL slave, 
      system memory and ISA slaves
    - 4 level of prefetch buffers from system memory for access by PCI 
      masters
    - Bursting capability for both PCI and CPU/VL bus
o   Intelligent PCI Interface
    - PCI 2.0 compliant
    - Synchronous or divide-by-two CPU clock
    - Hidden arbitration for up to four PCI masters
    - Supports PCI preemption and time-out function
    - Supports PCI master and slave initiated abort mechanism
    - Supports PCI lock function
    - Supports data parity generation for PCI master read cycles
    - Supports data parity checking for PCI master write cycles
    - Supports parity error and system error reporting on the PCI bus
    - Supports PCI configuration cycles
    - Interrupt steering and conversion to edge triggering for ISA 
      compatibility
o   PCI Compliant IO Characteristics
o   0.8um high speed and low power CMOS process
o   160pin PQFP package

**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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