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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98
Chips:         
[82443BX] (PAC) [82371EB] (PIIX4E)
CPUs:          Single or Dual P-II/P-III/Celeron
DRAM Types:    EDO SDRAM Reg SDRAM ESDRAM
Mem Rows:      6 EDO, 8 SDRAM, 8 Reg SDRAM, 8 ESDRAM
DRAM Density:  16Mbit 64Mbit 128Mbit*1
Max Mem:       1GB
ECC/Parity:    Both
AGP speed:     1x 2x
Bus Speed:     66 100 133*2
PCI Clock/Bus: 1/2 1/3 1/4*2 PCI 2.1


>*1 Only in C-1 and later steppings.

>*2 Exists  but unofficially. There is  no 1/2 divider  for AGP, 
    making AGP unstable in a 133MHz bus system. In this config. the 
    system is overclocked.

***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**Notes:
InfoWorld Apr 10, 1989 p42 - Video Severn and G-2 Will Merge to form
Headland Technology.
...affiliate of LSI logic.

According to:
http://www.vgamuseum.info/index.php/news/itemlist/category/15-headland-technology

Graphics chips were renamed from  GC*** to HT***. In this document any
part no. that differs only by  GC/HT have been assumed to be a renamed
part.

**GC101/102     12/16MHz PC/AT Compatible Chip Set             c:Feb88...
**GC101/102/103 12/16MHz PC/AT Compatible Chip Set + EMS 4.0   c:Jul89...
**GCK113        80386 AT Compatible Chip Set                   c:oct89...
**GCK181        Universal PS/2 Chip Set                        c:Mar89...
**HT11          Single 286 AT Chip [no datasheet]               <Aug90...
**HT12/+/A      Single 286 AT Chip with EMS support            c:Aug90...
**HT18          80386SX Single Chip                            c:Sep91...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94
***Info:...
***Versions:...
***Features:
o   VL to PCI Bridge
    - Combined with VT82C486 or VT82C496G for 80486SX/DX/DX2/DX4 based 
      PCI/VL/ISA Green-PC systems
    - Combined with VT82C530MV chip set for Pentium/P54C/M1 based 
      PCI/VL/ISA Green-PC Systems
o   Sophisticated Bridging Capabilities
    - Supports PCI master to PCI slave cycles
    - Supports PCI master to VL bus slave, system memory and ISA 
      slave cycles
    - Supports VL master including CPU to PCI slave cycles
    - Supports ISA master to VL or PCI slave cycles
    - Supports multiple accelerated decoding schemes from VL master 
      including CPU to PCI and ISA slaves
    - Supports CPUs with write-back level-one cache
    - Concurrent CPU and PCI operation
    - 4 level of CPU/VL to PCI post write buffers
    - Automatic detection of data streaming burst cycles from CPU/VL 
      to PCI bus
    - 4 level of post write buffers from PCI master to VL slave, 
      system memory and ISA slaves
    - 4 level of prefetch buffers from system memory for access by PCI 
      masters
    - Bursting capability for both PCI and CPU/VL bus
o   Intelligent PCI Interface
    - PCI 2.0 compliant
    - Synchronous or divide-by-two CPU clock
    - Hidden arbitration for up to four PCI masters
    - Supports PCI preemption and time-out function
    - Supports PCI master and slave initiated abort mechanism
    - Supports PCI lock function
    - Supports data parity generation for PCI master read cycles
    - Supports data parity checking for PCI master write cycles
    - Supports parity error and system error reporting on the PCI bus
    - Supports PCI configuration cycles
    - Interrupt steering and conversion to edge triggering for ISA 
      compatibility
o   PCI Compliant IO Characteristics
o   0.8um high speed and low power CMOS process
o   160pin PQFP package

**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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