[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?
***Info:
The SL9351 Memory Controller supports PC/ AT systems based on Intel's
80386DX microprocessor. It is a member of VIA's FlexSet family which
utilizes the same core logic across the entire PC/ AT spectrum. The
SL9351 is backward compatible with existing memory controllers for the
80386DX (SL9350). Boards designed using the SL9350 can be used with
the new SL9351 without modifications and with existing BIOS. In order
to take advantage of the SL9351's many new programmable features,
minor board modification and a modified BIOS is required for enhanced
performance.
The SL9351 offers the advanced memory control functions and features
needed to develop high performance PC/ AT systems without using
external TTL Logic. The SL9351 supports two-way page interleave mode
for 80386DX based designs. The Page interleave option can be enabled
or disabled using the configuration registers. All memory banks which
are interleaved use the same type of memory. Designers can enable the
staggered RAS option during refresh, which minimizes power surge. Both
pipeline and non-pipeline modes are supported by enabling or disabling
the next address controls, and providing ready at the correct time.
***Versions:...
***Features:...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96
***Notes:...
***Info:...
***Configurations:...
***Features:
o High Integration
- VT82C685 system controller
- VT82C687 data buffer
- VT82C586 PCI to ISA bridge
- Six TTLs for a complete main board implementation
o Flexible CPU Interface
- 64 bit Pentium-Pro CPU interface
- CPU external bus speed up to 66 MHz
- Supports Pentium-Pro CPU multi-phase bus protocol for split
transactions
- Supports four level deep in-order-queue and deferred transaction
- Supports APIC multiprocessor protocol
- GTL+TM bus driver and receiver compatible with Intel
specification
o Fast DRAM Controller
- Sixteen level (quadwords) of CPU to DRAM write buffers
- Sixteen level (quadwords) of DRAM to CPU read buffers
- Fast Page Mode/EDO/Burst EDO/Synchronous-DRAM support in a mixed
combination
- Mixed 1M/2M/4M/8M/16MxN DRAMs
- Supports 2-way bank-interleaving of 16 MB SDRAM
- Supports 2-way and 4-way bank-interleaving of 64 MB SDRAM
- 6 banks up to 1 GB DRAMs
- Flexible row and column addresses
- Optional bank-by-bank ECC and parity generation, detection, and
correction capability
- ECC with 1 bit error correction and multi-bit error detection
capability
- 3.3v and 5v DRAM without external buffers
- Burst read and write operation
- 5-1-1-1-1-1-1-1 back-to-back Burst EDO and Synchronous DRAM
transfer at 66 MHz
- 532 MB/s peak transfer rate for Burst EDO and Synchronous DRAMs
at 66 MHz
- 266 MB/s peak transfer rate for EDO DRAMs at 66 MHz
- BIOS shadow at 16 kB increment
- System management memory remapping
- Decoupled and burst DRAM refresh with staggered RAS timing
- Programmable refresh rate, CAS-before-RAS refresh and refresh
on populated banks only
o Intelligent PCI Bus Controller
- 32 bit 3.3/5v PCI interface
- Synchronous divide-by-two PCI bus interface
- PCI master snoop ahead and snoop filtering
- Concurrent PCI master/CPU/IDE operations
- Synchronous Bus to CPU clock with divide-by-two from the CPU
clock
- Automatic detection of data streaming burst cycles from CPU to
the PCI bus
- Sixteen levels (double-words) of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132 MByte/sec
- Sixteen levels (double-words) of post write buffers from PCI
masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM for
access by PCI masters
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Complete steerable PCI interrupts
- Supports CPU write-back forward to PCI master read to minimize
PCI read latency
- Supports CPU write-back merged with PCI master post-write to
minimize DRAM utilization
- Provides transaction timer to fairly arbitrate between PCI
masters
- Supports five PCI masters in addition to PCI-ISA/IDE/USB bridge
- PCI-2.1 compliant
o Enhanced Master Mode PCI IDE Controller with Extension to
UltraDMA-33
- Dual channel master mode PCI supporting four Enhanced IDE
devices
- Transfer rate up to 22 MB/sec to cover PIO mode 4 and multi-word
DMA mode 2 drives and beyond
- Extension to UltraDMA-33 interface for up to 33 MB/sec transfer
rate
- Sixteen levels (doublewords) of prefetch and write buffers
- Interlaced commands between two channels
- Bus master programming interface for SFF-8038 rev.1.0 and
Windows-95 compliant
- Full scatter and gather capability
- Support ATAPI compliant devices
- Support PCI native and ATA compatibility modes
- Complete software driver support
o Universal Serial Bus Controller
- USB v.1.0 and Intel Universal HCI v.1.1 compatible
- Eighteen level (doubleword) of data FIFOs with full scatter
and gather capabilities
- Root hub and two function ports with integrated physical
layer transceivers
- Legacy keyboard and PS2 mouse support
o Plug and Play Controller
- Dual interrupt and DMA signal steering with plug and play
control
- Microsoft Windows 95TM and plug and play BIOS compliant
o Sophisticated Power Management and OnNow/ACPI Unit
- Normal, doze, sleep, suspend and conserve modes
- System event monitoring with two event classes
- Two general purpose timers
- Sixteen general purpose output ports
- Seven external event input ports with programmable SMI condition
- Primary and secondary interrupt differentiation for individual
channels
- Clock throttling control
- Multiple internal and external SMI sources for flexible power
management models
- APM 1.2 compliant models
- Extension to OnNow and ACPI (Advanced Configuration and Power
Interface) support
o PCI to ISA Bridge
- Integrated 82C206 peripheral controller
- Integrated keyboard controller with PS2 mouse supports
- Integrated DS12885 style real time clock with extended 128 Byte
CMOS RAM
- Integrated USB controller with root hub and two function ports
- Integrated master mode enhanced IDE controller with enhanced
PCI bus commands
- PCI-2.1 compliant with delay transaction
- Four double-word line buffer between PCI and ISA bus
- Supports type F DMA transfers
- Fast reset and Gate A20 operation
- Edge trigger or level sensitive interrupt
- Flash EPROM, 2 MB EPROM and combined BIOS support
o Built-in Nand-tree pin scan test capability
o 0.5um mixed voltage, high speed and low power CMOS process
o 208 pin PQFP for VT82C685
o 208 pin PQFP for VT82C586
o 208 pin PQFP for VT82C687
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved