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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*UMC...
**UM82C230 286AT MORTAR Chip Set <91
***Info:
The UMC's MORTAR (286AT) Chip Set UM82C230 series provides an economic
alternative for building a reliable IBM PC/AT compatible system. A
commercial 12MHZ/0 wait state, 4MByte main memory system and
math-coprocessor can be easily built by using 3 VLSIs, 8 logic
components plus memory and processor.
The UM82C230 MORTAR chipset consists of the UM82C231 System/Memory
Controller, the UM82C232 Data/Address Buffer and the UM82C206
Integrated Peripherals Controller (IPC).
As shown in the System Block Diagram, [see datasheet] there are three
data buses: local data bus, AT data bus and peripheral data (XD) bus.
The local DRAM, EPROM and Numerical Processor are located on the local
data bus. The UM82C206 and 8042 Keyboard Controller sit on the XD bus.
The AT data bus was driven by the UM82C232 directly which conveys the
data to/from the AT Channel Adaptors.
The address bus architecture is also very simple; local CPU address
bus, local DRAM address bus (MA), peripheral address bus (XA) and AT
address bus. The local address bus is shared between CPU, UM82C231 and
UM82C206. The MA bus is used by the local DRAM only. Most of the
system board devices are attached to the XA bus, like UM82C232,
UM82C206, ROMs and 8042. Some AT address lines are driven by the
UM82C231 or UM82C232 directly; the others are buffered.
The UM82C231 provides synchronization and control signals for all
buses. The UM82C231 also distinguishes if the current cycle is local
memory cycle. Upon detecting that it is a local DRAM cycle, no AT
control signals are sent out to the AT channel. The UM82C231 is based
on the memory configurations to complete the current cycle with
fastest response. If the cycle is AT cycle, the UM82C231 sends out the
control signals sequentially which are then used by the adaptors or
system board devices to receive the write data or to send the fetched
data. Then, depending on the status signals sent back by the adaptors
or system board devices, the UM82C231 determines which kind of AT
cycles to perform: 8-bit, 16-bit, bus conversion, wait state insert,
or wait state cycle.
The UM82C232 Data/Address buffer provides the buffering and latching
between the CPU local data bus, AT bus and XD bus. The parity bit
generation and parity bit checking logic resides in the UM82C232 also.
During DMA cycles, the UM82C232 latches the address from XD, which is
sent by the UM82C206, and transfers to XA bus.
***Configurations:...
***Features:...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96
***Notes:...
***Info:
The VT82C680 Apollo-P6 is a high performance, cost-effective and
energy efficient chip set for the implementation of PCI/ISA desktop
and notebook personal computer systems based on the 64 bit Intel
Pentium-Pro super-scalar processors. The chipset supports multi-
Pentium-Pro configuration with Intel GTL+ driver and receiver inter-
face up to 66 MHz external CPU bus speed. The chipset supports the
Pentium-Pro CPU multi-phase bus protocols for split transactions, four
level deep in-order queue and deferred transactions for optimal CPU
throughput.
The VT82C680 chip set consists of the VT82C685 system controller, the
VT82C687 data buffer and the VT82C586 PCI to ISA bridge. The VT82C680
supports six banks of DRAMs up to 1 GB. The DRAM controller supports
Standard Page Mode DRAM, EDO-DRAM, Burst EDO-DRAM and Synchronous DRAM
in a flexible mixed/match manner. The Burst-EDO and Synchronous DRAM
allows zero wait state bursting between the DRAM and the VT82C687 data
buffers at 66 MHz. The six banks of DRAM allow arbitrary mixture of
1M/2M/4M/8M/16MxN DRAMs with optional bank-by-bank ECC and parity
support. The chipset supports sixteen level (quadwords) of CPU to DRAM
write buffers and sixteen level (quadwords) of DRAM to CPU read
buffers to maximize the CPU bus and DRAM utilization. The peak data
transfer rate for the EDO and Synchronous DRAM (or Burst EDO) DRAMs is
266 MB/s and 532 MB/s, respectively.
The VT82C680 supports 3.3/5v 32 bit PCI bus with 64 bit to 32 bit data
conversion. Sixteen levels (doublewords) of post write buffers are
included to allow for concurrent CPU and PCI operation. Consecutive
CPU addresses are converted into burst PCI cycles with Byte merging
capability for optimal CPU to PCI throughput. For PCI master
operation, sixteen levels (doublewords) of post write buffers and
thirty-two levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chipset also supports
enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize
snoop overhead. In addition, the chipset supports advanced features
such as snoop ahead, snoop filtering, CPU write-back forward to PCI
master and CPU write-back merged with PCI post write buffers to
minimize PCI master read latency and DRAM utilization. The VT82C586
PCI to ISA bridge supports four levels (doublewords) of line buffers,
type F DMA transfers and delay transaction to allow efficient PCI bus
utilization (PCI-2.1 compliant). The VT82C586 also includes integrated
keyboard controller with PS2 mouse support, integrated DS12885 style
real time clock with extended 128 Byte CMOS RAM, integrated master
mode enhanced IDE controller with full scatter and gather capability
and extension to 33 MB/sec UltraDMA-33 transfer rate, integrated USB
interface with root hub and two function ports with built-in physical
layer transceiver, and OnNow/ACPI compliant advanced configuration and
power management interface. A complete main board can be implemented
with only six TTLs.
The VT82C680 is ideal for high performance, high quality, high energy
efficient and high integration desktop and notebook PCI/ISA computer
systems.
***Configurations:...
***Features:...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
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