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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*OPTi...
**82C701 FireStar Plus c:97
***Notes:...
***Info:
Overview
This section describes the follow-on chip to the OPTi FireStar ACPI
solution, the FireStar Plus. The key features of this new product can
be summarized as follows.
o Mostly backward-compatible in pin function and register set with
FireStar ACPI (some PIO functions have been moved from critical
pins to improve timing)
o Implements ATA-33 (Ultra DMA) IDE Interface, with support for all
modes
o Supports 2.5V CPUs
o Incorporates MA13 support for 64Mb SDRAM chips
o Incorporates 64Mb EDO DRAM support
o Enables use of synchronous DRAM on all six banks (original
FireStar chip limited synchronous DRAM to the first four banks)
o Allows redefinition of many interface pins for better utilization
of chipset PIO features (many new function pins are easily
available)
Features
The following paragraphs describe the feature set changes between
FireStar ACPI and FireStar Plus.
Ultra DMA IDE Interface
The ATA33 specification for synchronous bus mastering IDE, also known
as Ultra DMA, is fully supported by FireStar Plus.
Synchronous DRAM on All Banks
The original FireStar chip supports synchronous DRAM only on RAS0-3#.
FireStar Plus also supports synchronous DRAM on RAS4-5#. The
additional functionality is selected through register bits that are
already defined on the FireStar ACPI part.
2.5V CPU Interface
FireStar Plus supports newer CPUs with I/O voltage requirements as low
as 2.5V. The pin redefinition is as follows.
o Pins E8, G5, T5, and W5 are now VCC_CPU and can be powered at 2.5V
or 3.3V.
o Pins K5, H22, and AB19 are now VCC_CORE and must always be powered
at 3.3V.
o Pin M5, CPUCLKIN, must receive a clock on the VCC_CPU plane. So if
a 2.5V CPU is used, this clock should also be 2.5V.
The 2.5V interface is a strap-selected option. It is selected by a
strap on pin B7 (new MA13 pin). If B7 is sensed low at reset, the CPU
interface is 3.3V; if sensed high along with TMS (pin AB5) low, the
CPU interface is 2.5V.
Redefinition of DRQ/DACK# Interface
The 7 pins assigned to DACK0-7# can be redefined to improve avail-
ability of PIO pins.
While the new definition only involves circuit modifications to the
DACK0-7# pins, the overall gain is much greater when used with the
82C602A Companion Chip in its Viper Note-book Mode A configuration.
o 8 power management inputs are now available, muxed in with the
DRQs and IRQ8# on the four EPMMUX pins.
o 7 full-featured PIO pins are available on the former FireStar
DRQ0-7 pins and IRQ8# pin. The number of pins is actually 8, but
is reduced b y 1 because one must be programmed as ATCLK/2.
o 12 PPWR outputs are generated by latching the SD bus lines from
PCTLH (FireStar PPWRL) and PCTLL (FireStar RSTDRV).
o The ISA bus RSTDRV signal is now generated by the 82C602A chip, so
that the FireStar RSTDRV pin can be used for PPWR generation
(power control latch control signal). If the extra PPWR signals
are not needed, the FireStar RSTDRV pin becomes useful as a full-
featured PIO pin.
Warnings
1. Until the Extended Mode option has been programmed, DACK3-7# will
be driving out against the signal input muxes. It is therefore
important to ensure that the logic will not be harmed by this
arrangement (the FireStar outputs safely accept being driven by
external logic in this mode).
2. EDACKEN is an option used to ensure proper ISA master operation.
It prevents the EDACK decoder from glitching its DACK# outputs during
EDACK switching. If ISA masters are not supported in the system, this
option is not needed (tie the EDACK line high on the 82C602A).
3. There are no provisions to block conflicts in case more than one
pin is programmed to the same function. For example, if a PIO pin is
programmed to be ACPI8-11, and the Extended Mode option also enables
EPMMUX1 to bring in ACPI8-11, the results are unpredictable.
***Configurations:...
***Features:...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*TI (Texas Instruments)...
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*Unresearched:...
*VIA...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98
***Notes:...
***info:...
***Configurations:...
***Features:
o General
- 492 BGA Package (35mm x 35mm )
- 2.5 Volt +/- 0.2V Core
- Supports separately powered 3.3V tolerant interface to CPU and
Memory
- Supports separately powered 5.0V tolerant interface to PCI bus
and Video interface
- 2.5V, 0.25um, high speed / low power CMOS process
- PC-98/99 compatible using VIA VT82C686A (352-pin BGA) south
bridge chip
- 66 / 100 MHz Operation
CPU Internal DRAM / PCI Comments
AGP VGC
100 MHz 66 MHz 100 MHz 33 MHz synchronous
(DRAM uses CPU clock)
66 MHz 66 MHz 66 MHz 33 MHz synchronous
(DRAM uses CPU clock)
66 MHz 66 MHz 100 MHz 33 MHz Up pseudo-synchronous
(DRAM uses MEM clock)
o Socket 7 Host Interface
- Supports all Socket-7 / Super-7 processors including 64-bit
Intel Pentium / Pentium with MMX , AMD 6K86 (K6 and K6-2),
Cyrix/IBM 6x86 / 6x86MX, IDT/Centaur C6, and Rise MP6 CPUs
- 66 / 100 MHz CPU "Front Side Bus"
- Supports 3.3V and sub-3.3V interface to CPU
- Built-in de-skew PLL (Phase Lock Loop) circuitry for optimal
skew control within and between clocking regions
- Cyrix/IBM 6x86 linear burst support
- AMD K6 and K6-2 write allocation support
- Supports CPU-to-DRAM write combining
- System management interrupt, memory remap and stop clock
mechanisms
o Advanced L2 Cache
- Direct map write-back or write-through secondary cache
- Pipelined burst synchronous SRAM (PBSRAM) cache support
- Flexible cache size: 0K / 256K / 512K / 1M / 2MB
- 32 byte line size to match the primary cache
- Integrated 8-bit tag comparator
- 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM accesses
up to 100 MHz
- Tag timing optimized (less than 4ns setup time) to allow
external tag SRAM implementation for most flexible cache
organization
- Sustained 3 cycle write access for PBSRAM access or CPU to
DRAM & PCI bus post write buffers up to 100 MHz
- Supports CPU single read cycle L2 allocation
- System and video BIOS cacheable and write-protect
- Programmable cacheable region
o Internal Accelerated Graphics Port (AGP) Controller
- AGP v2.0 compliant for 1x and 2x transfer modes
- Pipelined split-transaction long-burst transfers up to
533 MB/sec
- Eight level read request queue
- Four level posted-write request queue
- Thirty-two level (quadwords) read data FIFO (128 bytes)
- Sixteen level (quadwords) write data FIFO (64 bytes)
- Intelligent request reordering for maximum AGP bus utilization
- Supports Flush/Fence commands
- Graphics Address Relocation Table (GART)
- One level TLB structure
- Sixteen entry fully associative page table
- LRU replacement scheme
- Independent GART lookup control for host / AGP / PCI master
accesses
- Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport
driver support
o Concurrent PCI Bus Controller
- PCI bus is synchronous / pseudo-synchronous to host CPU bus
- 33 MHz operation on the primary PCI bus
- Supports up to five PCI masters
- Peer concurrency
- Concurrent multiple PCI master transactions; i.e., allow PCI
masters from both PCI buses active at the same time
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132Mbyte/sec
- PCI master snoop ahead and snoop filtering
- Six levels (double-words) of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Forty-eight levels (double-words) of post write buffers from
PCI masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM
for access by PCI masters
- Supports L1/L2 write-back forward to PCI master read to
minimize PCI read latency
- Supports L1/L2 write-back merged with PCI master post-write to
minimize DRAM utilization
- Delay transaction from PCI master reading DRAM
- Read caching for PCI master reading DRAM
- Transaction timer for fair arbitration between PCI masters
(granularity of two PCI clocks)
- Symmetric arbitration between Host/PCI bus for optimized
system performance
- Complete steerable PCI interrupts
- PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant
inputs
o High-Performance DRAM Controller
- 64-bit DRAM interface synchronous with host CPU (66//100 MHz)
or internal Memory Clock (100 MHz)
- Concurrent CPU and AGP access
- Supports both standard PC100 and "Virtual Channel" PC100
SDRAMs as well as FPG and EDO DRAMs
- Different DRAM types (FPG, EDO, and SDRAM) may be used in
mixed combinations
- Different DRAM timing for each bank
- Dynamic Clock Enable (CKE) control for SDRAM power reduction
- Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs
- 6 banks up to 768MB DRAMs
- Flexible row and column addresses
- 64-bit data width only
- 3.3V DRAM interface
- Programmable I/O drive capability for MA, command, and MD
signals
- Optional bank-by-bank ECC (single-bit error correction and
multi-bit error detection) or EC (error checking only) for
DRAM integrity
- Two-bank interleaving for 16Mbit SDRAM support
- Two-bank and four bank interleaving for 64Mbit SDRAM support
- Supports maximum 8-bank interleave (i.e., 8 pages open
simultaneously); banks are allocated based on LRU
- Seamless DRAM command scheduling for maximum DRAM bus
utilization (e.g., precharge other banks while accessing the
current bank)
- Four cache lines (16 quadwords) of CPU/cache to DRAM write
buffers
- Four quadwords of CPU/cache to DRAM read prefetch buffers
- Concurrent DRAM writeback
- Read around write capability for non-stalled CPU read
- Burst read and write operation
- 5-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM
- 6-1-1-1-2-1-1-1 back-to-back accesses for SDRAM
- BIOS shadow at 16KB increment
- Decoupled and burst DRAM refresh with staggered RAS timing
- Programmable refresh rate and refresh on populated banks only
- CAS before RAS or self refresh
o Sophisticated Power Management Features
- Independent clock stop controls for CPU / SDRAM, Internal AGP
and PCI bus
- PCI and AGP bus clock run and clock generator control
- Suspend power plane preserves memory data
- Suspend-to-DRAM and Self-Refresh operation
- Dynamic clock gating for internal functional blocks for power
reduction during normal operation
- Low-leakage I/O pads
o General Graphic Capabilities
- 64-bit Single Cycle 2D/3D Graphics Engine
- Supports 2 to 8 Mbytes of Frame Buffer located in System Memory
- Real Time DVD MPEG-2 and AC-3 Playback
- Video Processor
- I2C Serial Interface
- Integrated 24-bit 230MHz True Color DAC
- Extended Screen Resolutions up to 1600x1200
- Extended Text Modes 80 or 132 columns by 25/30/43/60 rows
- DirectX 6 and OpenGL ICD API
o High Performance rCADE3D Accelerator
- 32 entry command queue, 32 entry data queue
- 4Kbyte texture cache with over 90% hit rates
- Pipelined Setup/Texturing/Rendering Engines
- DirectDraw acceleration
- Multiple buffering and page flipping
o Setup Engine
- 32-bit IEEE floating point input data
- Slope and vertex calculations
- Back facing triangle culling
- 1/16 sub-pixel positioning
o Rendering Engine
- High performance single pass execution
- Diffused and specula lighting
- Gouraud and flat shading
- Anti-aliasing including edge, scene, and super-sampling
- OpenGL compliant blending for fog and depth-cueing
- 16-bit Z-buffer
- 8/16/32 bit per pixel color formats
o Texturing Engine
- D3D compressed texture formats DXT1 and DXT2
- Anisotropic texture filtering
- 1/2/4/8-bits per pixel compact palletized textures
- 16/32-bits per pixel quality non-palletized textures
- Pallet formats in ARGB 565, 1555, or 444
- Tri-linear, bi-linear, and point-sampled filtering
- Mip-mapping with multiple Level-Of-Detail (LOD) calculations
and perspective correction
- Color keying for translucency
o 2D GUI Engine
- 8/15/16/24/32-bits per pixel color formats
- 256 Raster Operations (ROPs)
- Accelerated drawing: BitBLTs, lines, polygons, fills,
patterns, clipping, bit masking
- Panning, scrolling, clipping, color expansion, sprites
- 32x32 and 64x64 Hardware Cursor
- DOS graphics and text modes
o DVD
- Hardware-Assisted MPEG-2 Architecture for DVD with AC-3
- Simultaneous motion compensation and front-end processing
(parsing, decryption and decode)
- Supports full DVD 1.0, VCD 2.0 and CD-Karaoke
- Microsoft DirectShow 2.x native support, backward compatible to
MCI
- No additional frame buffer requirements
- Dynamic frame and field de-interlace filtering for high quality
playback on VGA monitors (Bob and Weave)
- Tamper-proof software CSS implementation
- Freeze, Fast-Forward, Slow Motion, Reverse
- Pan-and-Scan support for 16:9 sequence
o Video Processor
- On-chip Color Space Converter (CSC)
- Anti-tearing via two frame buffer based capture surfaces
- Minifier for video stream compression and filtering
- Horizontal/vertical interpolation with edge recovery
- Dual frame buffer apertures for independent memory access for
graphics and video
- YUV 4:2:2/4:1:1/4:2:0 and RGB formats
- Capture / ZV Port to MPEG and video decoder
- Vertical Blank Interval for Intercast
- Overlay differing video and graphic color depths
- Display two simultaneous video streams from both internal AGP
and Capture / ZV Port
- Two scalers and Color Space Converters (CSC) for independent
windows
o Digital Flat Panel (DFP) Interface
- 85MHz DFP interface supports 1024x768 panels
- Allows external TMDS transmitter for advanced panel interfaces
o Testability
- Build-in NAND-tree pin scan test capability
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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