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**M1489/87 FinALi-486 PCI Chipset <Feb95
***Info:
ALi's M1489/M1487 PCI chipset is the most cost effective PCI solution
available. M1489/M1487 enables top-to-bottom PCI in 486 CPU systems,
offering superior price/performance for mainstream PCI-ISA systems.
M1489/M1487 highly integrates the DRAM controller, L2 cache control-
ler, Host, PCI, and ISA interface, as well as the standard ISA
functions: DMA controller, interrupt controller, timer/counter, RTC
(Real Time Clock), and keyboard controller. Additionally, M1489/M1487
incorporates the high performance Local Bus IDE allowing a system de-
signer to implement Local bus IDE with no additional cost. M1489/M1487
is a highly integrated solution requiring minimized TTL components,
enabling PCI-ISA designs at costs equal to or lower than comparable VL
Bus designs.
M1489 (Cache Memory PCI Controller: CMP) integrates the L2 cache con-
troller and the DRAM controller. The cache controller supports
write-back cache policies and cache size from 128K to 1M byte in an
interleaved or non-interleaved configuration. The DRAM controller
interfaces DRAM to the Host bus, PCI bus, and Link bus. M1489 can
support EDO 3/5V DRAM, standard DRAM, and flexible timing
select. M1489 also integrates intelligent Host to PCI, PCI to Host
buffer to achieve high performance. Also, M1489 provides the high
performance Local Bus IDE interface.
M1487 (ISA Bridge Controller: IBC) provides the bridge between the ISA
bus, PCI bus, and Host bus. IBC integrates the common I/O functions
found in today's ISA based systems: a seven channel DMA, two 82C59
interrupt controllers, 8254 timer/ counter, deep green function, and
control logic for NMI generation. IBC also has built-in 128 bytes RTC,
MC14069, KBC, and 7406. IBC also provides the decode for external
BIOS.
***Configurations:...
***Features:...
**M???? Genie, Quad Pentium [no datasheet, some info] c95...
**M1451/49 Aladdin (Pentium) [no datasheet] ?...
**M1511/12/13 Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23 Aladdin III 50-66MHz <Nov96...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97
***Info:...
***Configurations:...
***Features:
o PCI/ISA Green PC Ready
- Supports separately powered 3.3V (5V tolerant) interfaces to
system memory, AGP, and PCI bus
- Supports 3.3V and sub-3.3V interface to CPU
- PC-97 compatible using VT82C586B South Bridge with ACPI Power
Management
o High Integration
- Single chip implementation for 64-bit Socket-7-CPU, 64-bit
system memory, 32-bit PCI and 32-bit AGP interfaces
- Apollo VP3 Chipset: VT82C597 or VT82C597AT system controller
and VT82C586B PCI to ISA bridge
- Chipset includes UltraDMA-33 EIDE, USB, and Keyboard / PS2-Mouse
Interfaces plus RTC / CMOS on chip
o Flexible CPU Interface
- Supports 64-bit Pentium, AMD 5k86, AMD 6k86 and Cyrix 6x86 CPUs
- CPU external bus speed up to 66 MHz (internal 233MHz and above)
- Supports CPU internal write-back cache
- System management interrupt, memory remap and STPCLK mechanism
- Cyrix 6x86 linear burst support
- CPU NA# / Address pipeline capability
- 4 cache lines of CPU/cache-to-DRAM post-write buffers
- 4 quadwords of CPU/cache-to-DRAM read-prefetch buffers
o Advanced Cache Controller
- Direct map write back or write through secondary cache
- Pipelined burst synchronous SRAM (PBSRAM) cache support (with
global write enable feature)
- Flexible cache size: 0K / 256K / 512K / 1M / 2MB
- 32 byte line size to match the primary cache
- Integrated 10-bit tag comparator
- 3-1-1-1 read/write timing for PBSRAM access at 66 MHz
- 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM access at
66 MHz
- Sustained 3 cycle write access for PBSRAM access or CPU to DRAM
and PCI bus post write buffers at 66 MHz
- Data streaming for simultaneous primary and secondary cache line
fill
- System and video BIOS cacheable and write-protect
- Programmable cacheable region and cache timing
o AGP Controller
- AGP v1.0 compliant
- Supports SideBand Addressing (SBA) mode (non-multiplexed
address/data)
- Supports 133MHz 2X mode for AD and SBA signalling
- Pipelined split-transaction long-burst transfers up to 533 MB/
sec
- Eight level read request queue
- Four level posted-write request queue
- Thirty-two level (quadwords) read data FIFO (128 bytes)
- Sixteen level (quadwords) write data FIFO (64 bytes)
- Intelligent request reordering for maximum AGP bus utilization
- Supports Flush/Fence commands
o GART
- One level TLB structure
- Sixteen entry fully associative page table
- LRU replacement scheme
- Independent GART lookup control for host / AGP / PCI master
accesses
o Intelligent PCI Bus Controller
- PCI buses are synchronous to host CPU bus
- 33 MHz operation on the primary PCI bus
- 66 MHz PCI operation on the AGP bus
- PCI-to-PCI bridge configuration on the 66MHz PCI bus
- Separate data buffers for the two PCI buses
- Peer concurrency
- Concurrent multiple PCI master transactions; i.e., allow PCI
masters from both PCI buses active at the same time
- Allows PCI master access while ISA master/DMA is active
- PCI master snoop ahead and snoop filtering
- Five levels (double-words) of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132Mbyte/sec
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Forty-eight levels (double-words) of post write buffers from PCI
masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM for
access by PCI masters
- Supports L1/L2 write-back forward to PCI master read to minimize
PCI read latency
- Supports L1/L2 write-back merged with PCI master post-write to
minimize DRAM utilization
- Transaction timer for fair arbitration between PCI masters
(granularity of two PCI clocks)
- Symmetric arbitration between Host/PCI bus for optimized system
performance
- Complete steerable PCI interrupts
- PCI-2.1 compliant, 32 bit 3.3V PCI interface with 5V tolerant
inputs
o Advanced High-Performance DRAM Controller
- 66MHz DRAM interface
- Concurrent CPU and AGP access
- FP, EDO, SDRAM, and SDRAM-II
- 66MHz DDR (Double Data Rate) supported for SDRAM-II
(supports central and edge DQ, bidirectional DS, and optional
SDR write)
- Different DRAM types may be used in mixed combinations
- Different DRAM timing for each bank
- Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs
- 6 banks up to 1GB DRAMs
- Flexible row and column addresses
- 64-bit data width only
- 3.3V DRAM interface with 5V-tolerant inputs
- Optional bank-by-bank ECC (single-bit error correction and
multi-bit error detection) or EC (error checking only) for DRAM
integrity
- Two-bank interleaving for 16Mbit SDRAM support
- Two-bank and four bank interleaving for 64Mbit SDRAM support
(14 MA lines)
- Supports maximum 8-bank interleave (i.e., 8 pages open
simultaneously); banks are allocated based on LRU
- Seamless DRAM command scheduling for maximum DRAM bus utilization
(e.g., precharge other banks while accessing the current bank)
- Four cache lines (16 quadwords) of CPU/cache to DRAM write
buffers
- Concurrent DRAM writeback
- Read around write capability for non-stalled CPU read
- Burst read and write operation
- 5-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing
for EDO DRAMs at 66 MHz
- 6-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page for
SDRAMs at 66 MHz
- 5-2-2-2-3-2-2-2 back-to-back accesses for EDO DRAM at 66 MHz
- 6-1-1-1-3-1-1-1 back-to-back accesses for SDRAM at 66 MHz
- BIOS shadow at 16KB increment
- Decoupled and burst DRAM refresh with staggered RAS timing
- Programmable refresh rate, CAS-before-RAS refresh and refresh on
populated banks only
o Built-in NAND-tree pin scan test capability
o 3.3V, 0.5um, high speed / low power CMOS process
o 472 pin BGA Package
o Alternate pinouts available to optimally accommodate different PCB
form factors
- VT82C597 for ATX and NLX
- VT82C597AT for Baby AT and ATX
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
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