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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*Motorola...
*OPTi...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96
***Notes:...
***Info:...
***Configurations:...
***Features:
System
o 100% PC/AT compatible
o Supports 3.3V Intel Pentium 75/90/100/120 processors at bus
frequencies up to 66MHz
o Supports Cyrix 6x86 processor
DRAM
o Full 64-bit FPM/EDO DRAM controller
- Supports 2-2-2 EDO pipeline at 66MHz bus speed
- Supports 5V or 3.3V DRAM with-out buffers
- Supports up to 512MB
- Controls up to 6 banks
- Post write buffer
o Selectable current drive for DRAM bus
Cache
o L1 Cache supports write-through and write-back modes
o Power managed L2 Cache
- 64KB-2MB cache
- Write-back or write-through modes
- 2-1-1-1 synchronous cache cycles
- 3-1-1-1 pipelined synchronous cache cycles
- Combined tag/dirty SRAM option
ISA/VL/PCI Bus
o Integrated PCI bus with operation up to 33MHz; supports up to
three masters
o CLKRUN# support for PCI
o Distributed DMA support (software-based)
o 100% AT-compatible ISA bus; 3.3V or 5V operation, also supports
ISA bus masters
o VL bus support (slave only)
o Integrated Local Bus IDE supports four drives, which can be bus
masters, modes 4 and 5 supported
Power Management
o Advanced Power Management Unit
o Full CPU System Management Mode (SMM) support
o Full CPU power control through "clock throttling"
o Full system clock control, even CPU clock can be stopped during
APM doze mode
o Both hardware and software controlled power management
o Full peripheral power control
o 13 flexible peripheral timers
o Sixteen power control pins
o I/O trapping captures address and data
o Distributed DMA support (software-based)
o Full peripheral activity tracking
o Automatic peripheral power-up/power-down features
o Full suspend current leakage control
o 36 Power Management Interrupt (PMI) sources
o Eight external power management interrupt sources
o Supports SMBASE re-programmability that allows the cache to be
maintained during system management mode, avoiding cache fills
after returning from SMM
o Proprietary automatic internal pull-up/pull-down resistors
activated only when needed to reduce power consumption
Thermal Management
o Advanced Thermal Management Unit
o Internal mechanism tracks CPU activity and initiates cool down
mode before CPU temperature reaches a damaging level
o External sensor option
Packaging
o 82C556M Data Buffer
- 176 pin TQFP (0.5mm pin spacing)
o 82C557M System Controller
- 208 pin TQFP (0.5mm pin spacing)
o 82C558E Peripheral Controller
- 208 pin TQFP (0.5mm pin spacing)
82C602A RTC/Buffer Companion Chip
o Integrated Real-Time Clock
o Based on Benchmark Bq3285
o 256 bytes battery-backed memory
o Integrates multiplexing/demultiplexing logic, latches, and
buffers
o Eliminates most/all TTL in typical synchronous cache system
o 100 pin TQFP package (0.5mm pin spacing)
o Also available in 100 pin PQFP
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97
***Info:
The VT82C590 Apollo-VP2 is a high performance, cost-effective and
energy efficient chip set for the implementation of PCI/ISA desktop
and notebook personal computer systems based on the 64-bit
Pentium/AMD5K86/AMD6K86/Cyrix6X86 super-scalar processors.
The Apollo-VP2 chip set consists of the VT82C595 system controller
(328 pin BGA) and the VT82C586B PCI to ISA bridge (208 pin PQFP). The
VT82C595 system controller provides superior performance between the
CPU, optional synchronous cache, DRAM and the PCI bus with pipelined,
burst and concurrent operation. For pipelined burst synchronous SRAMs,
3-1-1-1-1-1-1-1 timing can be achieved for both read and write
transactions at 66 Mhz. Four cache lines (16 quadwords) of CPU/cache
to DRAM write buffers with concurrent write-back capability are
included in the chip to speed up the cache read and write miss cycles.
The VT82C595 supports six banks of DRAMs up to 512KB. The DRAM
controller supports Standard Page Mode DRAM, EDO DRAM and Synchronous
DRAM in a flexible mix / match manner. The Synchronous DRAM interface
allows zero wait state bursting between the DRAM and the data buffers
at 66Mhz. The six banks of DRAM can be composed of an arbitrary
mixture of 1M / 2M / 4M / 8M / 16MxN DRAMs. Each bank may be populated
with either 32bit or 64bit data width. The DRAM controller also
supports optional ECC (single-bit error correction and multi-bit
detection) capability.
The VT82C595 supports 3.3 / 5V 32-bit PCI bus with 64-bit to 32-bit
data conversion. Five levels (doublewords) of post write buffers are
included to allow for concurrent CPU and PCI operation. Consecutive
CPU addresses are converted into burst PCI cycles with byte merging
capability for optimal CPU to PCI throughput. For PCI master
operation, forty-eight levels (doublewords) of post write buffers and
sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chipset also supports
enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-
Multiple and Memory-Write-Invalid commands to minimize snoop
overhead. In addition, the chipset supports advanced features such as
snoop ahead, snoop filtering, L1 write-back forward to PCI master and
L1 write-back merged with PCI post write buffers to minimize PCI
master read latency and DRAM utilization. The VT82C586B PCI to ISA
bridge supports four levels (doublewords) of line buffers, type F DMA
transfers and delay transaction to allow efficient PCI bus utilization
and (PCI-2.1 compliant). The VT82C586B also includes an integrated
keyboard controller with PS2 mouse support, integrated DS12885 style
real time clock with extended 256 byte CMOS RAM, integrated master
mode enhanced IDE controller with full scatter and gather capability
and extension to UltraDMA-33 / ATA-33 for 33MB/sec transfer rate,
integrated USB interface with root hub and two function ports with
built-in physical layer transceivers, Distributed DMA support, and
OnNow / ACPI compliant advanced configuration and power management
interface. A complete main board can be implemented with only six
TTLs.
The VT82C590 chipset is ideal for high performance, high quality, high
energy efficient and high integration desktop and notebook PCI/ISA
computer systems.
***Configurations:...
***Features:...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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