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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:
The 50 MHz Intel486 DX  CPU-Cache Chip Set provides a high performance
solution  for  servers  and  high-end desktop  systems.   This  binary
compatible solution  has been optimized  to provide 50 MHz,  zero wait
state performance. The CPU-Cache chip set combines the 50 MHz Intel486
Microprocessor with  the 82495DX/82490DX cache  subsystem. It delivers
integer  performance of  41 V1.1  Dhrystone  MlPs and  a SPEC  integer
rating  of  27.9.  The  cache  subsystem  features  the 82495DX  Cache
Controller and the 82490DX Dual  Ported Data RAM.  Dual ported buffers
and registers  of the  82490DX allow the  82495DX Cache  Controller to
concurrently handle CPU bus, memory bus, and internal cache operations
for maximum performance.

The CPU-Cache Chip Set offers  many features that are ideal for multi-
processor  based systems.  The  Write-Back feature  provides efficient
memory  bus utilization  by reducing  bus traffic  through eliminating
unnecessary  writes  to main  memory.   The  CPU-Cache  chip set  also
supports MESI protocol and monitors  the memory bus to guarantee cache
coherency.

The 50  MHz Intel486  DX CPU and  82495DX/82490DX Cache  subsystem are
produced on  Intel's latest CHMOS  V process which  features submicron
technology and triple layer metal.

3.0 ARCHITECTURAL OVERVIEW
3.1 Introduction
The Intel486 CPU-cache chip  set provides a tightly coupled processing
engine  based on  the Intel486  microprocessor and  a  cache subsystem
comprised of  the 82495DX cache controller and  multiple 82490DX cache
components.   Figure 3.1  [see datasheet]  diagrams the  basic config-
uration.

The cache subsystem provides a  gateway between the CPU and the memory
bus. All CPU accesses that  can be serviced locally are transparent to
the memory bus and serve to avoid bus traffic.  As a result, the cache
chip  set  reduces memory  bus  bandwidth  to  both increase  Intel486
processor  performance and  support efficient  multiprocessor systems.
The  cache subsystem also  decouples the  CPU from  the memory  bus to
provide  zero-wait-state  operation at  high  clock frequencies  while
allowing relatively slow and inexpensive memories.

The  CPU-cache chip  set  prevents latency  and bandwidth  bottlenecks
across  a variety  of  uniprocessor and  multiprocessor designs.   The
processor’s  on-chip cache  supports  a  very wide  CPU  data bus  and
high-speed data  movement. The second-level cache  greatly extends the
capabilities of the on-chip cache resources, enabling a larger portion
of memory cycles to be satisfied independently of the memory bus.

3.2 CPU-Cache Chip Set Description
The chip set is comprised of three functional blocks: 

3.2.1 CPU
The chip  set includes a  special version of the  Intel486DX micropro-
cessor at  50 MHz.  The Intel486DX Microprocessor  Data Sheet provides
complete component specifications.

3.2.2 CACHE CONTROLLER
The 82495DX cache controller is  the main control element for the chip
set. providing  tags and line  states. and determining cache  hits and
misses. The 82495DX executes all  CPU bus requests and coordinates all
main memory accesses with the memory bus controller (MBC).

The 82495DX  controls the data  paths of the 82490DX  cache components
for cache hits and misses and furnishes the CPU with needed data.  The
controller  dynamically adds  wait  states as  needed  using the  most
recently used (MRU) prediction algorithm.

The 82495DX also performs memory bus snoop operations in shared memory
systems  and drives  the  cycle address  and  other attributes  during
memory bus accesses. Figure  3.2 [see datasheet] diagrams the 82495DX.

3.2.3 CACHE SRAM

Multiple  82490DX cache  components provide  the cache  SRAM  and data
path. Each component  includes the latches, muxes and  logic needed to
work in lock  step with the 82495DX to efficiently  serve both hit and
miss  accesses.  The 82490DX  components take  full advantage  of VLSI
silicon   flexibility   to  exceed   the   capabilities  of   discrete
implementations.  The  82490DX components support  zero-wait-state hit
accesses  and  concurrent  CPU  and  memory  bus  accesses,  and  they
replicate MRU  bits for autonomous  way prediction. During  memory bus
cycles. the 82490DX components act as a gateway between CPU and memory
buses. Figure 3.3 [see datasheet] diagrams an 82490DX cache component.

3.3 Secondary Cache Features

The 82495DX  cache controller and  82490DX cache components  provide a
unified, software  transparent secondary  data and  instruction cache.
The cache enables  a highspeed processor core  that provides efficient
performance even when paired with a significantly slower memory bus.

The secondary  cache interprets  CPU bus cycles  and can  service most
memory read and  write cycles without accessing main  memory.  I/O and
other special cycles are passed directly to the memory bus.  The cache
has a dual-port  structure that permits concurrent CPU  and memory bus
operation.

The 82495DX  cache controller  contains the 8K  tag entries  and logic
needed to support a cache as  large as 256K. Combinations of between 4
and 9 82490DX cache SRAMs are  used to create caches ranging from 128K
to 256K, with or without data parity.

The  MBC provides  logic  needed  to interface  the  CPU, 82495DX  and
82490DX  to the  memory  bus.   Because the  MBC  also affects  system
performance.  its design can be the basis of product differentiation.

***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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*VIA...
**VT82C580VPX  Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Flexible CPU Interface
    - Supports 64-bit Pentium, AMD 5k86, AMD 6k86 and Cyrix 6x86 CPUs
    - CPU external bus speed up to 75 MHz (asynchronous) or 66MHz 
      (synchronous) (internal 200Mhz and above)
    - Supports CPU internal write-back cache
    - System management interrupt, memory remap and STPCLK mechanism
    - Cyrix 6x86 linear burst support
    - CPU NA# / Address pipeline capability
o   Low Cost
    - PQFP packaging for low-cost implementation of 64-bit Pentium-
      CPU, 64-bit system memory, and 32-bit PCI
    - VT82C580 Apollo VPX Chipset:  VT82C585VPX system controller and 
      VT82C587VP Data Buffers
    - VT82C586B includes UltraDMA-33 EIDE, USB, and Keyboard / Mouse 
      Interfaces plus RTC / CMOS
    - Six TTLs for a complete main board implementation
o   PCI/ISA Green PC Ready
    - Supports 3.3V or 5V interface to CPU, system memory, and / or 
      PCI bus
    - Supports CPUs with internal voltages below 3.3V
    - PC-97 compatible using VT82C586B South Bridge with ACPI 
      Power Management
o   Advanced Cache Controller
    - Direct map write back or write through secondary cache
    - Pipelined burst synchronous SRAM (PBSRAM) cache support
    - Flexible cache size: 0K/256K/512K/1M/2MB
    - 32 byte line size to match the primary cache
    - Integrated 10-bit tag comparator
    - 3-1-1-1 read/write timing for PBSRAM access at 66/75 MHz
    - 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM access 
      at 66/75 MHz
    - Sustained 3 cycle write access for PBSRAM access or CPU to 
      DRAM and PCI bus post write buffers at 66/75 MHz
    - Data streaming for simultaneous primary and secondary cache 
      line fill
    - System and video BIOS cacheable and write-protect
    - Programmable cacheable region and cache timing
o   Fast DRAM Controller
    - Fast Page Mode/EDO/Synchronous-DRAM support in a mixed 
      combination
    - Mixed 1M/2M/4M/8M/16MxN DRAMs
    - 6 banks up to 512MB DRAMs
    - Flexible row and column addresses
    - 64-bit or 32-bit data width in arbitrary mixed combination
    - 3.3v and 5v DRAM without external buffers
    - Two-bank interleaving for 16Mbit SDRAM support
    - Two-bank and four bank interleaving for 64Mbit SDRAM support 
      (14 MA lines)
    - Four cache lines (16 quadwords) of CPU/cache to DRAM write 
      buffers
    - Concurrent DRAM writeback
    - Speculative DRAM access
    - Read around write capability for non-stalled CPU read
    - Burst read and write operation
    - 4-2-2-2 on page, 7-2-2-2 start page and 9-2-2-2 off page timing 
      for EDO DRAMs at 50/60 MHz
    - 5-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing 
      for EDO DRAMs at 66 MHz
    - 6-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page for 
      SDRAMs at 66 MHz
    - 5-2-2-2-3-1-2-2 back-to-back access for EDO DRAM at 66 MHz
    - 6-1-1-1-3-1-1-1 back-to-back access for SDRAM at 66 MHz
    - BIOS shadow at 16KB increment
    - Decoupled and burst DRAM refresh with staggered RAS timing
    - Programmable refresh rate, CAS-before-RAS refresh and refresh 
      on populated banks only
o   Intelligent PCI Bus Controller
    - 32 bit 3.3/5v PCI interface
    - Synchronous divide-by-two and asynchronous PCI bus interface
    - PCI master snoop ahead and snoop filtering
    - PCI master peer concurrency
    - Synchronous bus to CPU clock with divide-by-two from the CPU 
      clock
    - Automatic detection of data streaming burst cycles from CPU to 
      the PCI bus
    - Five levels (double-words) of CPU to PCI posted write buffers
    - Byte merging in the write buffers to reduce the number of PCI 
      cycles and to create further PCI bursting possibilities
    - Zero wait state PCI master and slave burst transfer rate
    - PCI to system memory data streaming up to 132Mbyte/sec
    - Forty-eight levels (double-words) of post write buffers from 
      PCI masters to DRAM
    - Sixteen levels (double-words) of prefetch buffers from DRAM 
      for access by PCI masters
    - Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
    - Complete steerable PCI interrupts
    - Supports L1 write-back forward to PCI master read to minimize 
      PCI read latency
    - Supports L1 write-back merged with PCI master post-write to 
      minimize DRAM utilization
    - Provides transaction timer to fairly arbitrate between PCI 
      masters
    - PCI-2.1 compliant
o   Built-in nand-tree pin scan test capability
o   0.6um mixed voltage, high speed / low power CMOS process
o   VT82C585VPX:  208-pin PQFP Package
o   VT82C587VP:  100-pin PQFP Package

**VT82C590     Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT  Apollo VP3, Single-Chip for Pentium with AGP  <10/03/97...
**VT82C598MVP  Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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